Abstract: A system for providing an award to a plurality of players is described herein. The system includes a plurality of gaming devices and a system controller coupled to each of the gaming devices. The system controller initiates a bonus game on a set of gaming devices. Each of the gaming devices included in the set is associated with a qualified player. The system controller selects a bonus game symbol for each qualified player from a predefined set of bonus game symbols and associates each selected bonus game symbol with the corresponding qualified player. The system controller also randomly selects a winning bonus game symbol from the predefined set of bonus game symbols, determines a number of winning qualified players associated with the winning bonus game symbol, and provides a bonus award to each of the winning qualified players.

Abstract: Certain embodiments provide systems and methods for awarding jackpots and disseminating information regarding jackpot awards in a gaming environment. Certain embodiments provide a method for announcing jackpot awards including detecting a jackpot awarded at a gaming terminal in the gaming system, determining satisfaction of an announcement criterion by the jackpot, and transmitting, upon satisfaction of the announcement criterion, a jackpot announcement to a group of one or more players satisfying an eligibility criterion. The jackpot announcement may include, for example, an opportunity to win an additional jackpot and/or an award of an additional jackpot. In certain embodiments, the announcement criterion identifies a jackpot sufficient to trigger a jackpot announcement and opportunity for an additional jackpot award. In certain embodiments, the eligibility criterion identifies one or more groups of one or more players who qualify for an opportunity for an additional jackpot.

Abstract: A system and method are disclosed for editing netlists described in a hardware description language (HDL). In one embodiment, a netlist is provided and a changes module is provided. The changes module contains a set of changes associated with the netlist. A tool, such as a netlist compiler, then edits the netlist using the changes described in the changes module. The changes module may be used on subsequent, or different, versions of the netlist where the netlist element changed by the changes module are the same. In this manner, repeated manual editing of a netlist, may be significantly reduced.

Abstract: Simultaneously increasing the effective frequency of scanning operations and increasing memory capacity can be achieved by multiplexing multiple state data into each tester memory location. A system includes a source for providing scan-in sequences of state data as input stimuli into a device under test (DUT) and expected scan-out sequences of state data. A vector processor receives the scan-in sequences and expected scan-out sequences and enables multiplexed state data exchanges in which the multiple multiplexed state data vectors are manipulated at the tester cycle rate, while the DUT manipulates the bits at its faster device cycle rate. For a multiplexing factor of m, the device cycle rate may be m times the tester cycle rate. The selection of the multiplexing factor is based upon the storage capacity of individual tester memory locations and upon enabling the effective vector exchange rate to be m times the tester cycle rate.

Abstract: A system and method are disclosed for editing netlists described in a hardware description language (HDL). In one embodiment, a netlist is provided and a changes module is provided. The changes module contains a set of changes associated with the netlist. A tool, such as a netlist compiler, then edits the netlist using the changes described in the changes module. The changes module may be used on subsequent, or different, versions of the netlist where the netlist element changed by the changes module are the same. In this manner, repeated manual editing of a netlist, may be significantly reduced.

Abstract: Simultaneously increasing the effective frequency of scanning operations and increasing memory capacity can be achieved by multiplexing multiple state data into each tester memory location. A system includes a source for providing scan-in sequences of state data as input stimuli into a device under test (DUT) and expected scan-out sequences of state data. A vector processor receives the scan-in sequences and expected scan-out sequences and enables multiplexed state data exchanges in which the multiple multiplexed state data vectors are manipulated at the tester cycle rate, while the DUT manipulates the bits at its faster device cycle rate. For a multiplexing factor of m, the device cycle rate may be m times the tester cycle rate. The selection of the multiplexing factor is based upon the storage capacity of individual tester memory locations and upon enabling the effective vector exchange rate to be m times the tester cycle rate.

Abstract: An integrated circuit is provided with Fully Automated Scan Testing (FAST)-lite flip-flop. The integrated circuit has data, scan in, master-hold, clock, scan-into-master, and master to-scan-out inputs. A first transistor circuit is connected to the data, master-hold, and clock inputs and has a first transistor circuit output. A second transistor circuit is connected to the can in and scan-into-master inputs and has a second transistor circuit output. A first flip-flop is connected to the first transistor circuit and second transistor circuit outputs and has a first flip-flop output. A third transistor circuit is connected to the second transistor circuit output and the master-to-scan-out input and has a third transistor circuit output. A second flip-flop latch is connected to the third transistor circuit output has a second flip-flop output. The FAST-lite flip-flop uses the normal functionality of the first flip-flop and second flip-flop to operate either in a normal mode or a test mode for scan testing.