Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that improve performance while reading memory. The method includes initializing an output of a of a sensing circuit to be a first logic high value, obtaining, from the memory, a first current corresponding to a memory bit stored in the memory, replicating the first current, determining whether the replicated first current is greater than a second current, and in response to determining that the replicated first current is greater than the second current, generating a second logic high value at the output of the sensing circuit.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve performance while reading a one-time programmable memory. An example apparatus includes: a voltage boost circuit including a first output, a second output, a first input configured to be coupled to a controller, a second input coupled to a first output of a decoder, a third input coupled to a second output of the decoder; and a multiplexer including a first input coupled to the first output of the voltage boost circuit, a second input coupled to the second output of the voltage boost circuit, a third input coupled to an array of memory, and an output coupled to a sensing circuit.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve performance while reading a one-time programmable memory. An example apparatus includes: a voltage boost circuit including a first output, a second output, a first input configured to be coupled to a controller, a second input coupled to a first output of a decoder, a third input coupled to a second output of the decoder; and a multiplexer including a first input coupled to the first output of the voltage boost circuit, a second input coupled to the second output of the voltage boost circuit, a third input coupled to an array of memory, and an output coupled to a sensing circuit.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that improve performance while reading memory. An example method includes initializing an output of a of a sensing circuit to be a first logic high value, obtaining, from the memory, a first current corresponding to a memory bit stored in the memory, replicating the first current, determining whether the replicated first current is greater than a second current, and in response to determining that the replicated first current is greater than the second current, generating a second logic high value at the output of the sensing circuit.

Abstract: The memory array contains two layers representing word lines of different rows. Each row contains multiple bit cells sharing the same word line. The two layers are stacked one on top of another to form a high density memory array.

Abstract: An actual sense amplifier senses a signal received on a bit line to generate a bit, and a latch latches the bit at a time point specified by a latch enable signal. A tracking circuit generates the latch enable signal in an appropriate time window. The tracking circuit may contain a dummy sense amplifier implemented similar to the actual sense amplifier and a dummy column from which the actual sense amplifier senses a signal received upon accessing the dummy memory array. The latch enable signal may be generated after the dummy sense amplifier generates a bit representing the sensed signal. The time taken by the dummy sense amplifier to generate the bit depends on the load offered by the dummy memory array. Accordingly, the dummy memory array is designed to offer sufficient load to ensure that the latch enable signal is generated in an appropriate time window.

Abstract: A sense amplifier which senses whether current is present on a bit line, and generates one logical value if current is present and another logical value if current is not present. As the sense amplifier can be implemented to generate such logical values with a current signal of low strength, memory arrays with correspondingly low drive strength can be implemented. As a result, memory systems which consume minimal power and having high density can be provided. In addition, as the sense amplifiers can operate without any reference signals, the implementation of sense amplifiers may be simplified.

Abstract: The write port circuits of a static memory cell includes a first conditional conduction path between a first output of the latch and ground active if and only if both a word line input and a write data true bit line input receive active signals. The write port circuit includes a second conditional conduction path between a second output of the latch and ground active if and only if both the word line and a write data complement bit line receive active signals. The first and second conditional conduction paths may be formed by a series connection of the source-drain paths of two transistors. In each conditional conduction path the gate of a first transistor receives a corresponding column signal and the gate of a second transistor is connected to the word line. The first and second transistors for each conduction path may be N-channel MOS transistors formed in a single N-type region. The first and second transistors forming the conditional conduction paths may be in either order.