Abstract: A circuit arrangement for combining a measure of the single phase error for a received data signal in a PSK demodulator with a measure of the direction of rotation of the receive data signal phasor between adjacent sample times for producing a timing phase error signal for controlling the phase of a local clock timing signal in the demodulator. In a demodulator producing a digital word defining differences between the phases of decoded phasors at adjacent sample times, a binary bit D.sub.k of the digital word may define the direction of rotation of the received signal phasor between the adjacent sample times. Sample values of the signal phase error signal in the demodulator are quantized into single binary bits E.sub.k indicating the sense of the signal phase error at sample times. In one circuit arrangement, binary bits E.sub.k and D.sub.k are combined in an exclusive-OR gate for producing a binary timing phase error bit M.sub.k.

Abstract: This 8-phase modulator comprises logic circuitry for converting tribits XYZ of input data into binary control signals D1, D2, D3 and D4 according to a prescribed plan, a pair of 4-phase signal generators responsive to associated pairs of control signals, and a signal source producing a pair of equal amplitude carrier signals of the same frequency and of phases which differ by 45.degree. for driving associated ones of the 4-phase generators 45.degree. out-of-phase. Equal amplitude vector signals from the two 4-phase generators are combined to produce a resultant vector signal which individually generates the phasors of an 8-phase signal set.

Abstract: Matched voltage-controlled resistances are provided across the drain-to-source channels of a pair of FET's, each FET having a gate electrode connected through an associated control resistor to the same one terminal of a source of DC control voltage; having a source electrode electrically connected to the same other terminal of the voltage source; and having an associated feedback resistor electrically connected between its drain and gate electrodes. The drain electrodes are preferably capacitively coupled to input or output terminals to prevent DC loading of the FET network by external circuitry. A resistor is also connected across the drain-to-source channel of each FET to limit the maximum value of net resistance presented thereby. The resistance of one of the control resistors is adjusted to have a value which causes the net drain-to-source resistance of the associated FET to have the same value as that of the other FET for a particular value of control voltage.