Abstract: An Algorithmic Reactive Testbench (ART) system is provided for the simulation/verification of an analog integrated circuit design. The ART system is a high level simulation/verification environment with a user program in which one or more analog testbenches are instantiated and operated as prescribed in an algorithmic reactive testbench program, and the properties of the unit testbenches (test objects) can be influenced by prior analysis of themselves or other tests. The test object may also contain various properties including information reflecting the status of the test object. The modification of a property of a test object is an act of communication in the ART system from the algorithmic reactive testbench program to the test object.

Abstract: An Algorithmic Reactive Testbench (ART) system is provided. The ART system is a high level verification environment with a user program in which on or more analog testbenches are instantiated and operated as prescribed in the program algorithm, and the properties of the unit testbenches (test objects) can be influenced by prior analysis of themselves or other tests. The results of the analysis may also affect the flow of the program itself. In the ART system, modification of the properties of a unit testbench occurs separately in the user program after definition of the unit testbench in the program (test object). A test object is a representation of a unit testbench along with its complete simulation setup and all associated data for the simulation. The test object may also contain various properties including information reflecting the status of the test object. The modification of a property of a test object is an act of communication in the ART system from the ART program to the test object.

Abstract: A biasing circuit is arranged to provide relatively well controlled startup and steady state behavior for a reference circuit such as noise immunity and reduced dependence on supplies. The biasing circuit initially employs an independent bias current for biasing the reference circuit at startup until a large enough bootstrapped (output voltage referenced) bias current can be generated that can take over the subsequent biasing of the circuit in the steady state. In one embodiment, a Power On Reset (POR) signal can be generated during the transition from an initial biasing of the reference circuit by the independent bias current to a subsequent steady state biasing provided by the bootstrapped bias current. Also, the assertion of the POR signal can be employed to turn off the transistors providing the independent bias current.