Abstract: The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved and hillock formation is significantly reduced by sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a plasma containing NH3 and N2, ramping up the introduction of trimethylsilane and then initiating deposition of a silicon carbide capping layer. Embodiments include treating the exposed surface of in-laid Cu with a soft NH3 plasma diluted with N2, shutting off the power, discontinuing the N2 flow and introducing He, then ramping up the introduction of trimethylsilane in three stages, and then initiating plasma enhanced chemical vapor deposition of a silicon carbide capping layer, while maintaining substantially the same temperature of 335° C. throughout plasma treatment and silicon carbide capping layer deposition. Embodiments also include forming Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than 3.9.

Abstract: A process for manufacturing a semiconductor device includes forming a first metallization level, forming a first etch stop layer, forming a low-k dielectric layer, forming a cap layer, depositing a resist, forming an opening; removing the resist, curing the dielectric material, etching the first etch stop layer, and filing the opening with metal. The first etch stop layer is formed over the first metallization level, and the low-k dielectric layer material is formed over the first etch stop layer. The cap layer is formed over the low-k dielectric layer material, and the resist is formed over the dielectric layer. Etching is used to form the opening. The resist is removed with an O2 stripping process. Curing of the dielectric material forms a dielectric layer and occurs after the resist is removed.