Abstract: In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.

Abstract: In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.

Abstract: A comprehensive method and system is disclosed for registering candidates, retrieving a self-assessment of their own skills and experiences, validating one or more of their skills and experiences leveraging third party websites and/or former managers or colleagues, associating those skills with focused and relevant video clips that permits immediate assessment of honesty and interpersonal communication skills in key areas of need, side by side comparisons between multiple candidates simultaneously and a simple “one button” click to arrange an interview or provide feedback to a candidate.

Abstract: A pulse width modulation (PWM) generator having asynchronous updating of its PWM duty cycle and/or period values allows immediate correction for the new PWM duty cycle and/or period values instead of waiting until the end of a PWM period to accept the new duty cycle and/or period values. This reduces the latency in a control loop when responding to changing system status, e.g., changes in PWM duty cycle. Also the PWM duty cycle is prevented from “running away” (e.g., missing a PWM cycle) if the PWM duty cycle timer/counter has advanced beyond an updated duty-cycle maximum value.

Abstract: Peripheral functions of an integrated circuit device may be pooled and dynamically mapped to available external input-output connections of the integrated circuit device by using a set of configuration registers. To provide system robustness, the configuration registers may implement various levels of write protection, error correction and monitoring circuitry. One or more peripheral output functions may be mapped to one or more external output connections. Not more than one output function may be active at the same time on the same output connection. Outputs and inputs may be mapped to the same external input-output connection with or without the output being controllable for placement into an inactive state, e.g., high impedance or open collector. When the input is required to receive external data over the external input-output connection, the output may be placed into the inactive state.

Abstract: Peripheral functions of an integrated circuit device may be pooled and dynamically mapped to available external input-output connections of the integrated circuit device by using a set of configuration registers. To provide system robustness, the configuration registers may implement various levels of write protection, error correction and monitoring circuitry. One or more peripheral output functions may be mapped to one or more external output connections. Not more than one output function may be active at the same time on the same output connection. Outputs and inputs may be mapped to the same external input-output connection with or without the output being controllable for placement into an inactive state, e.g., high impedance or open collector. When the input is required to receive external data over the external input-output connection, the output may be placed into the inactive state.

Abstract: A pulse width modulation (PWM) generator having asynchronous updating of its PWM duty cycle and/or period values allows immediate correction for the new PWM duty cycle and/or period values instead of waiting until the end of a PWM period to accept the new duty cycle and/or period values. This reduces the latency in a control loop when responding to changing system status, e.g., changes in PWM duty cycle. Also the PWM duty cycle is prevented from “running away” (e.g., missing a PWM cycle) if the PWM duty cycle timer/counter has advanced beyond an updated duty-cycle maximum value.