Abstract: An event-driven logic simulator provides for future evaluation events. Evaluation latencies are assigned to respective inputs of components based on component type. At least some of these latencies are positive and finite. When a signal status event specifies a change at an input associated with a positive latency, the function for the component is not evaluated at the present time. Instead, the evaluation is postponed to a future time equal to the present time plus the assigned latency. The evaluation is thus latent until the scheduled time becomes present. When multiple evaluation events are indicated for a common component output, a queue manager resolves the conflicts by discarding all but one of the evaluation events for that output. This approach minimizes redundant and superfluous evaluations during circuit simulation.

Abstract: A digital computer having stored therein a program receives information on pin locations, logic equations and timing delays from a plurality of inputs to a plurality of outputs of a representation of an electronic integrated circuit. A first representation of the electronic integrated circuit is constructed by the program based upon the input information. The first representation has a plurality of nodes interconnecting a plurality of first electronic logic circuit elements, with the first electronic logic circuit elements in the primitives of a first simulator.