Abstract: An output buffer array to a data output device in an integrated circuit. The output buffer array includes a plurality of output buffers connected together to a pair of parallel connected first and second voltage lines connected to a voltage supply circuit supplying a first voltage representative of a first logic state, and also to a pair of parallel connected first and second grounding lines connected to a grounding circuit supplying a second voltage representative of a second logic state. Each output buffer further includes logic and switching means which are devised in such a manner as to allow the noise occurred in one voltage or grounding line during the switching of the input data from one logic value to another to be dumped into another line such that the voltage transferred to the output of the output buffer is free from noise. This also allows the effect of ground bounce to be significantly reduced.

Abstract: The present invention relates to an improvement to an address transition detection (ATD) circuit in an IC chip, a method related to the improved ATD circuit is also disclosed. The improved ATD circuit applies a transfer gate and a lot of inverters to construct a new ATD circuit. Not only reduces power dissipation while an address transition is detecting, but less consumption on transistors is achieved. Each time when the logic state of an input pin is switching, the improved ATD circuit generates an inverting phase signal based on the switching; next, a transfer gate generates a driving signal for waking up the chip from idleness; a delaying circuit then generates a regular time interval for the chip to operate the task indicated by the varied address. At the end of the regular time interval, the chip returns to idleness again to wait another job's coming.