Abstract: A storage system and method for dynamic duty cycle correction are disclosed. In one embodiment, a controller of a storage system provides a clock signal to the memory, receives the clock signal back from the memory, monitors the duty cycle of the clock signal received back from the memory, and in response to the duty cycle of the clock signal received back from the memory not meeting a target value, adjusts the duty cycle of the clock signal provided to the memory so that the duty cycle of the clock signal received back from the memory better meets the target value. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A storage system and method for dynamic duty cycle correction are disclosed. In one embodiment, a controller of a storage system provides a clock signal to the memory, receives the clock signal back from the memory, monitors the duty cycle of the clock signal received back from the memory, and in response to the duty cycle of the clock signal received back from the memory not meeting a target value, adjusts the duty cycle of the clock signal provided to the memory so that the duty cycle of the clock signal received back from the memory better meets the target value. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A host power-on reset control circuit includes a comparator connected to receive both a divided version of a supply voltage and a reference voltage. The comparator generates and outputs a high digital state signal when the divided version of the supply voltage is at least as large as the reference voltage. The control circuit includes an output node connected to transmit a power-on reset control signal. The control circuit includes pulldown circuitry connected between the comparator output and the output node. The pulldown circuitry maintains the output node at a reset voltage level as the supply voltage rises to a host operational level, based on a signal present at the comparator output. The control circuit includes pullup circuitry connected between the supply voltage and the output node. The pullup circuitry maintains the output node at a non-reset voltage level after the supply voltage has risen to the host operational level.

Abstract: A host power-on reset control circuit includes a comparator connected to receive both a divided version of a supply voltage and a reference voltage. The comparator generates and outputs a high digital state signal when the divided version of the supply voltage is at least as large as the reference voltage. The control circuit includes an output node connected to transmit a power-on reset control signal. The control circuit includes pulldown circuitry connected between the comparator output and the output node. The pulldown circuitry maintains the output node at a reset voltage level as the supply voltage rises to a host operational level, based on a signal present at the comparator output. The control circuit includes pullup circuitry connected between the supply voltage and the output node. The pullup circuitry maintains the output node at a non-reset voltage level after the supply voltage has risen to the host operational level.

Abstract: Techniques are presented for reducing the DC voltage shift in a voltage regulator, particularly for high and ultra-high speed load switching operation. The regulator includes a power transistor, connected between an input supply voltage and an output node, and an error amplifier, having its output connected to control the gate of the output transistor, a first input connected to receive a reference voltage, and a second input connected to a feedback node. The regulator also includes a first resistance, connected between the feedback node and ground, and also a second resistance, a third resistance, and a first capacitance, where the feedback node is connected to the output node through a combination of the first capacitance in parallel with the second resistance and in series with the third resistance.