Abstract: A battery circuit board includes a substrate, a first trace configured to receive a voltage and forming a first closed loop around a perimeter of the substrate, and a second trace forming a second closed loop around the perimeter of the substrate. The battery circuit board also includes an electrical assembly configured to determine a presence of an electrolyte on the battery circuit board in response to a short circuit between the first closed loop of the first trace and the second closed loop of the second trace.

Abstract: An input device includes a plurality of sensor electrodes and a processing system that is operable in at least a first mode or a second mode. The processing system is configured to receive an input current from a pair of the sensor electrodes. When operating the first mode, the processing system is configured to measure a capacitance across the pair of sensor electrodes based on the received input current. When operating the second mode, the processing system is configured to measure a resistance between the pair of sensor electrodes based on the received input current.

Abstract: Methods and associated processing systems are disclosed for acquiring gain mismatch values and offset mismatch values corresponding to a plurality of analog-to-digital converters (ADCs). One method comprises coupling receiver circuitry of a processing system with a capacitive sensor comprising a plurality of sensor electrodes, the receiver circuitry comprising a plurality of ADCs, each ADC of the plurality of ADCs coupled with one or more respective sensor electrodes of the plurality of sensor electrodes. The method further comprises, while at least a portion of transmitter circuitry of the processing system is disabled, acquiring measurements using each ADC of the plurality of ADCs; and storing, using the acquired measurements, a plurality of offset mismatch values in a memory of the processing system. The processing system is operable to apply the plurality of offset mismatch values to capacitive measurements acquired using the plurality of ADCs.

Abstract: Embodiments herein provide input devices that include a display panel on which a discrete capacitive sensor is disposed to form a capacitive sensing region. The capacitive sensor includes a plurality of sensor electrodes that are used to generate capacitive sensing signals indicating user interaction with the input device. Moreover, the input device includes analog interference detection circuitry for mitigating the negative impact of display noise on capacitive sensing. In one embodiment, the input device includes a reference circuit which is capacitively coupled to a display noise source and outputs a reference voltage that biases a charge integrator in a receiver channel used for capacitive sensing. In another embodiment, the input device includes a current conveyor coupled to an idle transmitter electrode of the sensor electrodes which outputs a correction current to a receiver channel to cancel a display noise current injected into the receiver channel.

Abstract: An input device includes a plurality of sensor electrodes and a processing system that is operable in at least a first mode or a second mode. The processing system is configured to receive an input current from a pair of the sensor electrodes. When operating the first mode, the processing system is configured to measure a capacitance across the pair of sensor electrodes based on the received input current. When operating the second mode, the processing system is configured to measure a resistance between the pair of sensor electrodes based on the received input current.

Abstract: An example apparatus for converting a plurality of analog signals to a plurality of digital signals includes: a plurality of successive approximation (SAR) analog-to-digital converters (ADCs) each including a first input configured to receive a respective one of the plurality of analog signals, a second input configured to receive a reference signal, and an output configured to provide a respective one of the plurality of digital signals; and a shared cycle LSB generator coupled to the plurality of SAR ADCs and configured to provide the reference signal shared by the plurality of SAR ADCs.

Abstract: Methods and associated processing systems are disclosed for acquiring gain mismatch values and offset mismatch values corresponding to a plurality of analog-to-digital converters (ADCs). One method comprises coupling receiver circuitry of a processing system with a capacitive sensor comprising a plurality of sensor electrodes, the receiver circuitry comprising a plurality of ADCs, each ADC of the plurality of ADCs coupled with one or more respective sensor electrodes of the plurality of sensor electrodes. The method further comprises, while at least a portion of transmitter circuitry of the processing system is disabled, acquiring measurements using each ADC of the plurality of ADCs; and storing, using the acquired measurements, a plurality of offset mismatch values in a memory of the processing system. The processing system is operable to apply the plurality of offset mismatch values to capacitive measurements acquired using the plurality of ADCs.

Abstract: Embodiments herein describe input devices that include receivers for sampling capacitive sensing signals that perform continuous-time demodulation. An input device is provided that includes a plurality of sensor electrodes in a sensing region of the input device and a processing system coupled to the plurality of sensor electrodes and configured to generate a first measurement of a capacitive sensing signal acquired using a first sensor electrode of the plurality of sensor electrodes during a first time period, that comprises effects of a first modulated signal driven onto at least one of the plurality of sensor electrodes, the first measurement generated at a first sensing frequency based on a clock signal; periodically dither the clock signal; and adjust a demodulation frequency based on the dithered clock signal to generate a second measurement of the capacitive sensing signal during a second time period at the first sensing frequency based on the dithered clock signal.

Abstract: Embodiments herein describe input devices that include receivers for sampling capacitive sensing signals that perform continuous-time demodulation. An input device is provided that includes a plurality of sensor electrodes in a sensing region of the input device and a processing system coupled to the plurality of sensor electrodes and configured to generate a first measurement of a capacitive sensing signal acquired using a first sensor electrode of the plurality of sensor electrodes during a first time period, that comprises effects of a first modulated signal driven onto at least one of the plurality of sensor electrodes, the first measurement generated at a first sensing frequency based on a clock signal; periodically dither the clock signal; and adjust a demodulation frequency based on the dithered clock signal to generate a second measurement of the capacitive sensing signal during a second time period at the first sensing frequency based on the dithered clock signal.

Abstract: Embodiments herein provide input devices that include a display panel on which a discrete capacitive sensor is disposed to form a capacitive sensing region. The capacitive sensor includes a plurality of sensor electrodes that are used to generate capacitive sensing signals indicating user interaction with the input device. Moreover, the input device includes analog interference detection circuitry for mitigating the negative impact of display noise on capacitive sensing. In one embodiment, the input device includes a reference circuit which is capacitively coupled to a display noise source and outputs a reference voltage that biases a charge integrator in a receiver channel used for capacitive sensing. In another embodiment, the input device includes a current conveyor coupled to an idle transmitter electrode of the sensor electrodes which outputs a correction current to a receiver channel to cancel a display noise current injected into the receiver channel.

Abstract: Embodiments herein provide electronic devices that include a charge pump coupled to a split reservoir capacitor which includes at least two discrete capacitors. Further, the discrete capacitors are coupled together by a switch (e.g., a transistor) which is controlled by an output regulator. In one embodiment, the output regulator monitors an output voltage of the charge pump and the split reservoir capacitor to determine when the output differs from a predetermined target voltage. When the switch isolates the two capacitors, the charge pump can continue to add charge to a first one of the discrete capacitors. Thus, when the output regulator detects a dip in the output voltage and activates the switch to reconnect the two discrete capacitors, the first discrete capacitor has extra charge which can decrease the time needed to bring the output voltage back to the target voltage.

Abstract: In an example, a processing system for an electronic device, such as a capacitive sensing device, includes a reservoir capacitor configured to store charge from a charge pump, and a control circuit configured to operate the charge pump at irregular intervals to transfer charge to the reservoir capacitor.

Abstract: A discrete-time harmonic rejection mixer, an input device, and methods for using the same are described herein. In one example, a discrete-time harmonic rejection mixer includes a switched-capacitor network and a switch controller. The switched-capacitor network includes first, second, and third switched capacitor sub-circuits, each including a pair of capacitors and a set of switches. The switch controller is coupled to the switched-capacitor network, and is configured to operate the sets of switches. More specifically, the switch controller is configured to operate the sets of switches in an out of phase manner to produce the harmonic rejection effect. Capacitance values for the first pair of capacitors are roughly equal to capacitance values for the third pair of capacitors. An input device, method, and harmonic rejection circuit exhibiting the above features are provided as examples.

Abstract: Various embodiments provide a processing module that calibrates a current-mode baseline correction system to account for features in an input device that lead to “offset” in output of a charge integrator used for sensing presence of an input object. The offset is a difference between a common mode voltage, which is the average voltage output of the charge integrator over a sensing cycle and a mid-rail voltage midway between high and low power supply voltages. Calibration is performed by adjusting an N-side and/or P-side current flow duration parameter until common mode voltage falls within a low offset window in which the offset is deemed to be sufficiently close to the mid-rail voltage. The resulting duration parameters are stored and used for current-mode baseline corrections when operating an associated sensor electrode for capacitive sensing.

Abstract: A digital to analog convertor comprises an output line; first, second and third pluralities of capacitors; and first and second bridge capacitors. The first plurality of capacitors is coupled in parallel with one another, coupled with the output line, and comprises a first least significant bit capacitor of a first capacitance value. The second plurality of capacitors is coupled in parallel with one another, coupled with the output line, and comprises a second capacitor of the first capacitance value. The third plurality of capacitors is coupled in parallel with one another, coupled with the output line, and comprises a third capacitor of the first capacitance value. The first bridge capacitor bridges the output line between the first plurality of capacitors and the second plurality of capacitors. The second bridge capacitor bridges the output line between the second plurality of capacitors and the third plurality of capacitors.

Abstract: In an example, a processing system for an electronic device, such as a capacitive sensing device, includes a reservoir capacitor configured to store charge from a charge pump, and a control circuit configured to operate the charge pump at irregular intervals to transfer charge to the reservoir capacitor.

Abstract: Various embodiments provide a processing module that calibrates a current-mode baseline correction system to account for features in an input device that lead to “offset” in output of a charge integrator used for sensing presence of an input object. The offset is a difference between a common mode voltage, which is the average voltage output of the charge integrator over a sensing cycle and a mid-rail voltage midway between high and low power supply voltages. Calibration is performed by adjusting an N-side and/or P-side current flow duration parameter until common mode voltage falls within a low offset window in which the offset is deemed to be sufficiently close to the mid-rail voltage. The resulting duration parameters are stored and used for current-mode baseline corrections when operating an associated sensor electrode for capacitive sensing.

Abstract: Disclosed herein are techniques related to a discrete-time harmonic rejection mixer. The discrete-time harmonic rejection mixer includes a switched-capacitor network and a switch controller. The switched-capacitor network includes first, second, and third switched capacitor sub-circuits, each including a pair of capacitors and a set of switches. The switch controller is coupled to the switched-capacitor network, and is configured to operate the sets of switches. More specifically, the switch controller is configured to operate the sets of switches in an out of phase manner to produce the harmonic rejection effect. Capacitance values for the first pair of capacitors are roughly equal to capacitance values for the third pair of capacitors. An input device, method, and harmonic rejection circuit exhibiting the above features are provided as examples.