Abstract: An infrared sensing array having a detector array, a readout circuit, and processing circuitry. The detector array includes first and second subarrays having different sensitivities associated therewith for detecting different brightness level ranges. The sensitivities of the subarrays are determined by sensing circuit elements in the readout circuit. As a result of the subarrays of different sensitivities, the composite dynamic range covered by the array is greater than the individually dynamic ranges of the subarrays.

Abstract: An amplifier circuit 12 for an infrared detector 10 in a detector array formed on a large-scale integrated structure. The amplifier circuit is fabricated along with the detector on the structure and includes an amplifier stage capacitively coupled 14 to the detector 10 and an output stage. A switching FET 16 is provided to selectively couple the detector to an external biasing source and another switching FET 24 is provided to reset the amplifier stage after an integration period. In one embodiment the output stage 28 includes a storage capacitor 30 selectively coupled to the amplifier stage by a switching FET 32. In another embodiment the output encoding stage 28 includes a two-gate FET 32 to control the voltage on a storage capacitor 30. The two-gate FET controls a voltage source which periodically pulses and drains the capacitor. One FET gate is connected to the amplifier stage output and the other is connected to a clocking signal.

Abstract: An infrared detector assembly is disclosed which includes a photosensitive layer (111) and a first planar contact structure (113) conductively coupled to the photosensitive layer for collecting charge carriers generated by radiation incident on the photosensitive layer. The detector assembly further includes a second planar contact structure (119) substantially coextensive with and separated from the first planar contact structure. A dielectric layer (115) separates the first and second planar contact structures. The first and second planar contact structures and the dielectric structure form a feedback capacitor which is integral with the detector assembly and which provides feedback capacitance for an externally provided amplifier.

Abstract: An amplifier circuit 12 for an infrared detector 10 in a detector array formed on a large-scale integrated structure. The amplifier circuit is fabricated along with the detector on the structure and includes an amplifier stage capacitively coupled 14 to the detector 10 and an output stage. A switching FET 16 is provided to selectively couple the detector to an external biasing source and another switching FET 24 is provided to reset the amplifier stage after an integration period. In one embodiment the output stage 28 includes a storage capacitor 30 selectively coupled to the amplifier stage by a switching FET 32. In another embodiment the output encoding stage 28 includes a two-gate FET 32 to control the voltage on a storage capacitor 30. The two-gate FET controls a voltage source which periodically pulses and drains the capacitor. One FET gate is connected to the amplifier stage output and the other is connected to a clocking signal.

Abstract: A new technique, and output encoding circuits using that technique, are disclosed for interfacing between a semiconductor IR detector 23 and associated output electronics 24, 25, 26, which technique and circuits transfer a charge packet onto a sense capacitor 22 that previously stored a reset level signal. The resulting stepped signal change, or delta, in the voltage present on that capacitor 22 is employed as the output signal.

Abstract: A new technique, and output encoding circuits using that technique, are disclosed for interfacing between a semiconductor IR detector 23 and associated output electronics 24, 25, 26 which technique and circuits transfer a charge packet onto a sense capacitor 22 that previously stored a reset level signal. The resulting stepped signal change, or delta, in the voltage present on that capacitor 22 is employed as the output signal.

Abstract: A correlated quadruple sampling processor for improved signal-to-noise ratio in the output of a charge-coupled device (CCD) is comprised of: switching means for momentarily clamping a CCD signal line at a first reference level A before a CCD data pulse and then obtaining a first data sample B with respect to the reference A during a CCD data pulse, and storing the positive sample B-A; switching means for momentarily clamping the CCD signal line a second time at the level C during the presence of the CCD data pulse and then obtaining a second data sample D with respect to the reference level C after the CCD data pulse, and storing the negative sample D-C; and means for obtaining the difference between the stored samples +(B-A) and -(D-C), thus increasing the net signal amplitude by a factor of about 2 while the noise would be increased by only a factor of .sqroot.2 since there will be no correlation in the noise between the double samples +(B-A) and -(D-C) effectively added.