Abstract: A program memory controller unit includes apparatus for the execution of a software pipeline procedure in response to a predetermined instruction. The apparatus provides a prolog, a kernel, and an epilog state for the execution of the software pipeline procedure. In addition, in response to a predetermined condition, the software pipeline procedure can be terminated early. An interrupt state is provided to permit the servicing of an interrupt.

Abstract: A program memory controller unit includes apparatus for the execution of a software pipeline loop procedure in response to a predetermined instruction. The apparatus provides a prolog, a kernel, and an epilog state for the execution of the software pipeline procedure. In addition, in response to a predetermined condition, the software pipeline procedure can be terminated early. A second software procedure can be initiated prior to the completion of first software procedure. An SPEXIT instruction is provided to permit the software pipeline program to terminate upon the identification of a preselected condition. The SPEXIT instruction is placed in the instruction sequence to insure that response to the instruction occurs after the prolog procedure has been completed. The SPEXIT instruction, upon identification of the preselected condition, results in the software pipeline loop procedure entering an idle state.