Abstract: This invention relates to a clock sequencing apparatus which allows for clock stoppage at the end of a particular clock sequence without a false decoding of clock pulses at the beginning of what would have been the next clock sequence. This result is accomplished by providing a multi-state sequential apparatus having more states than clock phases. The apparatus will detect a stop condition on the last clock phase of a clock sequence and instead of changing to the state associated with the first clock phase of the next clock sequence, it will instead change state to one or more additional "dead time" states which will allow other logic circuitry to discontinue gating of the clock phases before the apparatus returns to the state associated with the first phase of the next clock sequence. The apparatus will then remain at the state associated with the first phase of the next clock sequence until the clock is restarted and the process is repeated.