Abstract: In accordance with at least one embodiment, credit-based flow control for high-speed interfaces is provided. Decoupling (separation) of high speed interface reference clocks from the interface data rates is enabled. Such decoupling allows consolidation of reference clocks used for high speed interfaces, thereby enabling one reference clock to be used for multiple interfaces having different data rates. It also results in reduced buffer resource (memory) requirements, and reduced system latency. In redundant systems it also simplifies the direct vs. spare selection mechanism.

Abstract: A clock regeneration circuit and method including an asynchronous clock signal input to a meta-stability filtering circuit, a synchronous clock signal input to the meta-stability filtering circuit with a frequency lower than the asynchronous clock signal, and being over-sampled and rate adapted to the asynchronous clock signal, an edge detector detecting an edge of the output of the meta-stability filtering circuit, a regenerated clock signal output therefrom, and a clock regeneration stage receiving an input that is the edge-detected output.

Abstract: A Weighted Random Early Detection (WRED) algorithm is described. The WRED algorithm provides fairness to responsive TCP and non-responsive UDP traffic at a buffer of a communications system. Because TCP traffic is responsive to congestion occurrences while UDP traffic is not, without controls, UDP will monopolize the buffer bandwidth. This invention solves the problem by applying congestion control alogrithms to TCP and UDP traffic separately. Discard thresholds for UDP traffic are dynamically modified in a manner that limits UDP traffic to a provisioned percentage of the buffer's available bandwidth, while a traditional WRED algorithm is applied to TCP traffic.

Abstract: A method for identifying faulty modules within telecommunication devices, such as ATM switches, involves generating and attaching verification codes, such as a CRC or checksum codes, to data packets at an upstream location determining the integrity of the verification codes at each of multiple downstream location within a telecommunication device; and signaling an error condition where a corrupted data packet has been detected. A verification code may be written to a field of a data packet which is not used while the packet is in transit through the telecommunication device.

Abstract: A clock regeneration circuit and method including an asynchronous clock signal input to a meta-stability filtering circuit, a synchronous clock signal input to the meta-stability filtering circuit with a frequency lower than the asynchronous clock signal, and being over-sampled and rate adapted to the asynchronous clock signal, an edge detector detecting an edge of the output of the meta-stability filtering circuit, a regenerated clock signal output therefrom, and a clock regeneration stage receiving an input that is the edge-detected output.

Abstract: Addressing error detection systems and methods are disclosed. A target address is written to a memory in an electronic system and subsequently output on an address path through which the memory is addressable. An addressing error is detected by determining whether the target address output on the address path is detected at the memory. Address detection at the memory involves storing the target address, monitoring the address path for the target address, and providing an address detection indication based on whether the target address is detected on the address path. The address detection indication may be provided, for example, by setting a flag in a data structure which is stored in the memory.

Abstract: In accordance with at least one embodiment, credit-based flow control for high-speed interfaces is provided. Decoupling (separation) of high speed interface reference clocks from the interface data rates is enabled. Such decoupling allows consolidation of reference clocks used for high speed interfaces, thereby enabling one reference clock to be used for multiple interfaces having different data rates. It also results in reduced buffer resource (memory) requirements, and reduced system latency. In redundant systems it also simplifies the direct vs. spare selection mechanism.

Abstract: A hybrid IP/ATM NT and method are provided for hybrid IP/ATM network termination. While traversing a DSLAM, ATM traffic over ATM network infrastructure and GigE/IP traffic over GigE/IP network infrastructure may be recast into crossover GigE/IP traffic and crossover ATM traffic respectively, and routed to the opposite kind of network infrastructure with use of the IP/ATM NT and hybrid IP/ATM network termination.

Abstract: A metastability filtering circuit comprising: a sampling circuit for sampling a first clock signal with a second clock signal to produce a sampled first clock signal, the first clock signal being synchronous to an interface between first and second systems; an edge detection circuit coupled to the sampling circuit for receiving the sampled first clock signal and for producing a rate adapted first clock signal; a delay circuit coupled to the edge detection circuit for receiving the rate adapted first clock signal and for producing first and second clock enable signals, the second clock enable signal being a delayed version of the first clock enable signal; and, a shift register clocked by the second clock signal and having first and second sequential registers enabled by the first and second clock enable signals, respectively, for receiving an input signal from the first system at the first register and providing a filtered output signal to the second system from the second register, wherein the filtered outpu

Abstract: A metastability filtering circuit comprising: a sampling circuit for sampling a first clock signal with a second clock signal to produce a sampled first clock signal, the first clock signal being synchronous to an interface between first and second systems; an edge detection circuit coupled to the sampling circuit for receiving the sampled first clock signal and for producing a rate adapted first clock signal; a delay circuit coupled to the edge detection circuit for receiving the rate adapted first clock signal and for producing first and second clock enable signals, the second clock enable signal being a delayed version of the first clock enable signal; and, a shift register clocked by the second clock signal and having first and second sequential registers enabled by the first and second clock enable signals, respectively, for receiving an input signal from the first system at the first register and providing a filtered output signal to the second system from the second register, wherein the filtered outpu

Abstract: Systems and methods for monitoring frequencies of periodic electrical signals are disclosed. According to one technique, a first and second counters are respectively clocked by a first periodic electrical signal to be monitored and a second periodic electrical, and a threshold detector resets one of the counters when a count of the other counter crosses a reset threshold and determines whether a frequency error has occurred based on whether a count of the one of the counters crosses an alarm threshold. Another technique according to an embodiment of the invention also involves clocking counters with respective periodic electrical signals, although error detection is based on whether the counts of the counters cross respective associated thresholds in other than a particular sequence with respect to each other.

Abstract: Addressing error detection systems and methods are disclosed. A target address is written to a memory in an electronic system and subsequently output on an address path through which the memory is addressable. An addressing error is detected by determining whether the target address output on the address path is detected at the memory. Address detection at the memory involves storing the target address, monitoring the address path for the target address, and providing an address detection indication based on whether the target address is detected on the address path. The address detection indication may be provided, for example, by setting a flag in a data structure which is stored in the memory.

Abstract: Systems and methods for protecting against memory addressing errors are disclosed. When data is to be written to a storage location in a memory, address protection information is calculated based on an address of the storage location, and combined address and data protection information is calculated based on both the address protection information and the data. The data and the combined address and data protection information are stored in the storage location. During a read operation, data and combined address and data protection information are retrieved from a storage location at a read address. Address protection information is recalculated based on the address from which data is to be read, and an addressing error is detected where the recalculated address protection information does not match original address protection information upon the basis of which the retrieved combined address and data protection information was calculated.

Abstract: Systems and methods for monitoring frequencies of periodic electrical signals are disclosed. According to one technique, a first and second counters are respectively clocked by a first periodic electrical signal to be monitored and a second periodic electrical, and a threshold detector resets one of the counters when a count of the other counter crosses a reset threshold and determines whether a frequency error has occurred based on whether a count of the one of the counters crosses an alarm threshold. Another technique according to an embodiment of the invention also involves clocking counters with respective periodic electrical signals, although error detection is based on whether the counts of the counters cross respective associated thresholds in other than a particular sequence with respect to each other.

Abstract: A Weighted Random Early Detection (WRED) algorithm is described. The WRED algorithm provides fairness to responsive TCP and non-responsive UDP traffic at a buffer of a communications system. Because TCP traffic is responsive to congestion occurrences while UDP traffic is not, without controls, UDP will monopolize the buffer bandwidth. This invention solves the problem by applying congestion control alogrithms to TCP and UDP traffic separately. Discard thresholds for UDP traffic are dynamically modified in a manner that limits UDP traffic to a provisioned percentage of the buffer's available bandwidth, while a traditional WRED algorithm is applied to TCP traffic.

Abstract: A system for implementing time stamp related features in a real time stamp distribution system is discussed. The distribution system derives a real time stamp (RTS) at a master timekeeping network element and distributes the RTS to associated network elements by way of a number of distribution techniques. Under certain network conditions, the real time stamp may not reach one or more of the network elements at the valid real time. In the present system, the network elements are able to derive a local time based on timing information recorded at the network element. Thus the system can detect an error in the time stamp delivered to a network element and can correct the time stamp utilizing a local time stamp feature.

Abstract: A method for identifying faulty modules within telecommunication devices, such as ATM switches, involves generating and attaching verification codes, such as a CRC or checksum codes, to data packets at an upstream location determining the integrity of the verification codes at each of multiple downstream location within a telecommunication device; and signaling an error condition where a corrupted data packet has been detected. A verification code may be written to a field of a data packet which is not used while the packet is in transit through the telecommunication device.

Abstract: A method for identifying faulty modules within telecommunication devices, such as ATM switches, involves generating and attaching verification codes, such as CRC or checksum codes, to data packets, such as ATM cells, at an upstream location, determining the integrity of the verification codes at each of multiple downstream location within a telecommunication device; and signaling an error condition where a corrupted data packet has been detected. A verification code may be written to a filed of a data packet which is not used while the ATM cell is in transit through the telecommunication device, thereby identifying a faulty module device without adversely affecting throughput.

Abstract: A method for verifying the integrity of data payloads of ATM cells passing through a switching device involves computing a payload integrity verification code for the payload portion of an ATM cell. The payload integrity verification code may be generated according to any error detection or error correction scheme. Preferably, the payload integrity verification code is stored in a portion of the standard ATM cell header which is not used while the cell is passing through the switching device. Preferably the payload integrity verification code is stored in all, or a portion of, the virtual path identifier or virtual connection identifier fields. The invention allows for the immediate identification of cells having corrupted payload data. Different actions may be taken on the detection of errors in the ATM cell header and ATM cell payloads respectively.