Abstract: Some embodiments of the present invention relate to a semiconducting device that includes an interposer having a fold which divides the interposer into a first section and a second section. A first die is attached to a first surface of the interposer at the first and second sections of the interposer. The semiconducting device further includes a contact that is attached to the first surface of the interposer at the first section and the second section. A second die is attached to a second surface of the interposer such that the second die is stacked onto the first die and is electrically coupled to the first die by the contact and conductive paths that are part of the interposer.

Abstract: Some embodiments of the present invention relate to a semiconducting device that includes an interposer having a fold which divides the interposer into a first section and a second section. A first die is attached to a first surface of the interposer at the first and second sections of the interposer. The semiconducting device further includes a contact that is attached to the first surface of the interposer at the first section and the second section. A second die is attached to a second surface of the interposer such that the second die is stacked onto the first die and is electrically coupled to the first die by the contact and conductive paths that are part of the interposer.

Abstract: Some embodiments of the present invention relate to a semiconducting device that includes an interposer having a fold which divides the interposer into a first section and a second section. A first die is attached to a first surface of the interposer at the first and second sections of the interposer. The semiconducting device further includes a contact that is attached to the first surface of the interposer at the first section and the second section. A second die is attached to a second surface of the interposer such that the second die is stacked onto the first die and is electrically coupled to the first die by the contact and conductive paths that are part of the interposer.

Abstract: The method of testing a memory array of SRAM cells each of which includes memory transistors, bit and bit# lines, precharge circuitry, and an output test terminal involving the steps of connecting selected bit and bit# lines of selected SRAM cells to the output test terminal, disconnecting the memory transistors of the selected SRAM cells from the bit and bit# lines, disconnecting the bit and bit# lines from the precharge circuitry, enabling the column select circuitry to select the columns of the selected SRAM cells, applying a preselected level voltage to the output test terminal, and measuring any current which flows.