Patents by Inventor Steve Felix
Steve Felix has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9083446Abstract: Method and receiver for processing a signal in a wireless communication system in which the signal comprises a sequence of chips. The signal is receive data at least one rake finger and sampled. There is a time spacing t1 between successive samples less than the time spacing tc between successive chips in the signal. Channel conditions on the channel are estimated and based on estimated channel conditions by the following steps: monitoring timing of the signal on one of the at least one rake finger to determine a time difference between the timing of the signal on the one of the at least one rake finger and the timing of the generation of the samples, the determined time difference being a multiple of t2, where t2<t1; aligning the timing of the generation of the samples with the timing of the signal on the one of the at least one rake finger to within a timing range t2.Type: GrantFiled: September 23, 2010Date of Patent: July 14, 2015Assignee: ICERA INC.Inventors: Steve Allpress, Steve Felix, Abdelkader Medles
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Patent number: 9052897Abstract: Method and computing system for controlling a supply voltage in the computing system. A voltage related indication for use in setting the supply voltage of the computing system is stored, and a supply voltage is set for the computing system based on the stored voltage related indication. A crash of the computing system is detected, and in dependence thereon, an adjusted indication is determined for use in the computing system. An adjusted supply voltage is set based on the adjusted indication, and the adjusted indication is stored for further use of the computing system.Type: GrantFiled: February 22, 2011Date of Patent: June 9, 2015Assignee: Nvidia Technology UK LimitedInventors: Steve Felix, Pete Cumming
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Patent number: 9026069Abstract: A method, device and computer program product is provided for sending a data signal and a clock signal between a radio frequency circuit of a device and a baseband circuit of the device, the radio frequency circuit being configured for at least one of transmission and reception of radio signals in a radio frequency band, where the clock signal has a clock frequency Fc. The method comprises selecting the clock frequency Fc to be a rational multiple of the 0.270833 MHz symbol rate of the Global System for Mobile Communications (GSM) standard and a rational multiple of the 3.84 MHz chipping rate of the Wideband Code Division Multiple Access (WCDMA) interface. The clock frequency Fc is selected such that the clock signal can be generated using a 38.4 MHz or 19.2 MHz reference clock signal, a non-fractional Phase Locked Loop clock multiplier and an output divider, without first having to divide down the reference clock signal.Type: GrantFiled: April 8, 2011Date of Patent: May 5, 2015Assignee: Nvidia Technology UK LimitedInventors: Abdellatif Bellaouar, Steve Felix, Hamid Safiri
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Patent number: 8817894Abstract: A method of sending a data signal and a clock signal between a radio frequency circuit of a device and a baseband circuit of the device. The method comprises: determining whether at least one of the data signal and the clock signal is disturbing in that it has a harmonic within the radio frequency band. If it is determined that at least one of the data signal and the clock signal is disturbing, the method further comprises: scrambling the at least one disturbing signal to flatten the spectrum thereof for frequencies below the clock frequency FC, setting a respective at least one indicator to indicate that the at least one disturbing signal has been scrambled, and sending the at least one scrambled signal between the radio frequency circuit and the baseband circuit. The method further comprises, subsequent to the step of sending the at least one scrambled signal, descrambling the at least one scrambled signal if the respective at least one indicator is set.Type: GrantFiled: March 4, 2011Date of Patent: August 26, 2014Assignee: Nvidia Technology UK LimitedInventor: Steve Felix
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Patent number: 8723577Abstract: Method, circuitry and device for spreading a clock signal in which the clock signal is received at an input of a variable delay line, the clock signal having been generated by a clock signal generator. In one embodiment, for each edge of the clock signal, the delay introduced by the variable delay line is set in accordance with a stored delay value. For each of a plurality of consecutive edges of the clock signal, the stored delay value is either incremented or decremented based on a randomly generated value for that edge. A spread version of the clock signal is output from the variable delay line, wherein each edge of the spread version of the clock signal is delayed by the respective delay that is set for that edge of the clock signal.Type: GrantFiled: July 20, 2012Date of Patent: May 13, 2014Assignee: Nvidia CorporationInventor: Steve Felix
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Patent number: 8723571Abstract: Integrated circuit and method for generating a clock signal, the integrated circuit comprising (i) a frequency locked loop comprising a voltage controlled oscillator configured to receive a control input and to generate a clock signal determined by the control input; and (ii) a microprocessor configured to be powered by a supply voltage and to receive the clock signal generated by the voltage controlled oscillator. The integrated circuit is configured to use the supply voltage as the control input, such that the clock signal is determined by the supply voltage.Type: GrantFiled: February 22, 2011Date of Patent: May 13, 2014Assignee: Nvidia Technology UK LimitedInventor: Steve Felix
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Publication number: 20140051365Abstract: A method, device and computer program product is provided for sending a data signal and a clock signal between a radio frequency circuit of a device and a baseband circuit of the device, the radio frequency circuit being configured for at least one of transmission and reception of radio signals in a radio frequency band, where the clock signal has a clock frequency Fc. The method comprises selecting the clock frequency Fc to be a rational multiple of the 0.270833 MHz symbol rate of the Global System for Mobile Communications (GSM) standard and a rational multiple of the 3.84 MHz chipping rate of the Wideband Code Division Multiple Access (WCDMA) interface. The clock frequency Fc is selected such that the clock signal can be generated using a 38.4 MHz or 19.2 MHz reference clock signal, a non-fractional Phase Locked Loop clock multiplier and an output divider, without first having to divide down the reference clock signal.Type: ApplicationFiled: April 8, 2011Publication date: February 20, 2014Applicant: NVIDIA TECHNOLOGY UK LIMITEDInventors: Abdellatif Bellaouar, Steve Felix, Hamid Safiri
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Publication number: 20130021075Abstract: Method, circuitry and device for spreading a clock signal in which the clock signal is received at an input of a variable delay line, the clock signal having been generated by a clock signal generator. In one embodiment, for each edge of the clock signal, the delay introduced by the variable delay line is set in accordance with a stored delay value. For each of a plurality of consecutive edges of the clock signal, the stored delay value is either incremented or decremented based on a randomly generated value for that edge. A spread version of the clock signal is output from the variable delay line, wherein each edge of the spread version of the clock signal is delayed by the respective delay that is set for that edge of the clock signal.Type: ApplicationFiled: July 20, 2012Publication date: January 24, 2013Applicant: NVIDIA CORPORATIONInventor: Steve Felix
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Publication number: 20120328049Abstract: A method of sending a data signal and a Downlink Uplink clock signal between a radio frequency circuit of a device and a baseband circuit of the device. The method comprises: determining whether at least one of the data signal and the clock signal is disturbing in that it has a harmonic within the radio frequency band. If it is determined that at least one of the data signal and the clock signal is disturbing, the method further comprises: scrambling the at least one disturbing signal to flatten the spectrum thereof for frequencies below the clock frequency FC, setting a respective at least one indicator to indicate that the at least one disturbing signal has been scrambled, and sending the at least one scrambled signal between the radio frequency circuit and the baseband circuit. The method further comprises, subsequent to the step of sending the at least one scrambled signal, descrambling the at least one scrambled signal if the respective at least one indicator is set.Type: ApplicationFiled: March 4, 2011Publication date: December 27, 2012Applicant: NVIDIA TECHNOLOGY UK LIMITEDInventor: Steve Felix
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Publication number: 20120313678Abstract: Integrated circuit and method for generating a clock signal, the integrated circuit comprising (i) a frequency locked loop comprising a voltage controlled oscillator configured to receive a control input and to generate a clock signal determined by the control input; and (ii) a microprocessor configured to be powered by a supply voltage and to receive the clock signal generated by the voltage controlled oscillator. The integrated circuit is configured to use the supply voltage as the control input, such that the clock signal is determined by the supply voltage.Type: ApplicationFiled: February 22, 2011Publication date: December 13, 2012Applicant: NVIDIA TECHNOLOGY UK LIMITEDInventor: Steve Felix
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Publication number: 20120311374Abstract: Method and computing system for controlling a supply voltage in the computing system. A voltage related indication for use in setting the supply voltage of the computing system is stored, and a supply voltage is set for the computing system based on the stored voltage related indication. A crash of the computing system is detected, and in dependence thereon, an adjusted indication is determined for use in the computing system. An adjusted supply voltage is set based on the adjusted indication, and the adjusted indication is stored for further use of the computing system.Type: ApplicationFiled: February 22, 2011Publication date: December 6, 2012Applicant: NVIDIA TECHNOLOGY UK LIMITEDInventors: Steve Felix, Pete Cumming
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Publication number: 20110075773Abstract: Method and receiver for processing a signal in a wireless communication system in which the signal comprises a sequence of chips. The signal is receive data at least one rake finger and sampled. There is a time spacing t1 between successive samples less than the time spacing tc between successive chips in the signal. Channel conditions on the channel are estimated and based on estimated channel conditions by the following steps: monitoring timing of the signal on one of the at least one rake finger to determine a time difference between the timing of the signal on the one of the at least one rake finger and the timing of the generation of the samples, the determined time difference being a multiple of t2, where t2<t1; aligning the timing of the generation of the samples with the timing of the signal on the one of the at least one rake finger to within a timing range t2.Type: ApplicationFiled: September 23, 2010Publication date: March 31, 2011Applicant: ICERA INC.Inventors: Steve Allpress, Steve Felix, Abdelkader Medles
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Patent number: 7796700Abstract: According to an embodiment of the invention, a method and system is disclosed for determining log-likelihood ratios for a coded set of individual bits (40) of a quadrature amplitude modulation (QAM) codeword. In the method at most two constant values (33,35) may be determined to perform a set of predetermined functions, the output of each of function is based on the constant values and at least one received component corresponding to the codeword, to determine log-likelihood ratios (37) for each individual bit of the set of individual bits of the codeword. The QAM codeword may correspond to at least a portion of a signal of a wireless device, such as a mobile third-generation device operating according to a Wideband Code-Division Multiple Access (WCDMA) standard.Type: GrantFiled: October 26, 2005Date of Patent: September 14, 2010Assignee: Icera Inc.Inventors: Steve Allpress, Steve Felix, Carlo Luschi