Abstract: The disclosure provides a PCI Express Scaled Port, a computing device and a method of communicating between PCI Express components. In one embodiment, the PCI Express Scaled Port includes: (1) an interface configured to communicate flow control negotiating packets with another PCI Express Port and (2) a FCC Controller configured to generate the flow control negotiating packets, wherein the flow control negotiating packets include a flow control credit for PCI Express packets and a scaling factor for the flow control credit.

Abstract: A clock generator chip, a PCI Express port and a computing device control board are provided herein. In one embodiment the clock generator chip includes: (1) a clock generator configured to generate a reference clock signal for a component in response to a clock request from the component, (2) a reference clock pin configured to provide the reference clock signal and (3) a pair of sideband signal pins configured to receive and transmit sideband packets between the component and the clock generator chip.

Abstract: The disclosure provides a PCI Express Scaled Port, a computing device and a method of communicating between PCI Express components. In one embodiment, the PCI Express Scaled Port includes: (1) an interface configured to communicate flow control negotiating packets with another PCI Express Port and (2) a FCC Controller configured to generate the flow control negotiating packets, wherein the flow control negotiating packets include a flow control credit for PCI Express packets and a scaling factor for the flow control credit.

Abstract: A clock generator chip, a PCI Express port and a computing device control board are provided herein. In one embodiment the clock generator chip includes: (1) a clock generator configured to generate a reference clock signal for a component in response to a clock request from the component, (2) a reference clock pin configured to provide the reference clock signal and (3) a pair of sideband signal pins configured to receive and transmit sideband packets between the component and the clock generator chip.

Abstract: Embodiments of the present invention provide methods, systems, and computer readable media for input output memory management unit (IOMMU) two-layer addressing in the context of memory address translations for I/O devices. According to an embodiment, a method includes translating a guest virtual address (GVA) to a corresponding guest physical address (GPA) using a guest address translation table according to a process address space identifier associated with an address translation transaction associated with an I/O device, and translating the GPA to a corresponding system physical address (SPA) using a system address translation table according to a device identifier associated with the address translation transaction.

Abstract: A system and method for facilitating measurement of environmental conditions such as might be used in emergencies or other situational awareness applications. The method includes dispersing several networked nodes in a region, the nodes being coupled to one or more sensors, and then employing the one or more sensors to sense one or more environmental conditions and providing sensed data in response thereto. In a more specific embodiment, the region exhibits a fire, and the method further includes utilizing the sensed data to predict fire conditions, such as fire movement and temperature. A controller may be employed to selectively adjust power to one or more sensors based on predetermined priorities associated with sensed data output from the one or more sensors.