Abstract: A system and corresponding method for measuring relative timing of signal events in at least one measurement signal includes input circuitry for receiving such a measurement signal. The input circuitry may include a comparator configured to convert the measurement input signal into a binary timing signal that is indicative of selected transitions, or signal events, in the measurement signal. The original measurement signal, or subsequently generated timing signal, is then provided to signal splitting circuitry that is configured to split such signal a predetermined number of times and to generate a plurality of data streams whose frequency level is lower than the frequency level of the original measurement signal.

Abstract: A method and apparatus for use in seismic prospecting are disclosed. The method comprises partitioning a plurality of converted split shear-wave data resulting from a common event and recorded at a plurality of azimuths and a plurality of offsets as a function of the azimuths and offsets; separating fast and slow split shear-wave wavefields in the partitioned data; deriving at least one attribute of at least one of the separated fast and slow shear-wave wavefields; and analyzing the derived attribute. The apparatus comprises, in one aspect, a program storage medium encoded with instruction that perform the method when executed by a computing device or a computer programmed to perform the device.

Abstract: A test circuit and test technique for scan testing integrated circuits is disclosed. The test circuit includes a drive 1 or drive 0 scan element which utilizes fewer transistors than conventional scan latches. The testing technique utilizes the clock input to the latches in the ICs for propagating data through the latches. The test circuit and test techniques may be used with microprocessors and particularly RISC microprocessors. The test technique includes coupling a drive 1 or drive 0 element to a logic element coupled to a general latch. The drive 1 or drive 0 scan element allows the general latch to be clocked by a clock signal such as a .phi.1 clock signal or .phi.2 clock signal.