Abstract: A memory fabrication apparatus includes a pair of targets arranged so as to be spaced apart from one another within a closed vacuum vessel, each target of said pair of targets having a sputtering surface facing the sputtering surface of the other target of said pair of targets; and substrate holder adapted to receive facing target sputtering a CMO material on an electrode.

Abstract: An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n? source region. A heavily doped p+ region known as a “halo” is disposed in the channel adjacent the heavily doped n+ drain. The floating gate is spaced away from the channel region by a generally thin tunnel oxide. A lightly doped source with a graded source/channel junction reduces source side CHE generation. In one variation, a thicker oxide between the source and the floating gate reduces CHE injection from the source side. A heavily doped drain with a halo implant in the channel adjacent the drain enhances drain side CHE generation.

Abstract: A method is disclosed to effectively achieve a low deposition temperature of CMO memory materials by depositing the CMO memory material at relatively low temperatures that give an amorphous film, then to later melt and re-crystallize the CMO memory material with a laser (laser annealing).

Abstract: A method is disclosed to effectively achieve a low deposition temperature of CMO memory materials by facing target sputter deposition of the CMO memory material at relatively low temperatures that give an amorphous film. Subsequently, the CMO material can be melt and re-crystallized with a laser (laser annealing).

Abstract: A memory array contains memory cells designed to be erased using Fowler-Nordheim (“FN”) tunneling through the channel area, and programmed using either channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). To reduce disturbance of the floating gate potential of unselected memory cells during programming operations and read operations, the unselected word lines are brought to a negative potential rather than ground potential. To reduce disturbance of the floating gate potential of unselected memory cells during FN erase operations, the unselected word lines are brought to a positive potential rather than ground potential.

Abstract: A memory array contains memory cells designed to be erased using Fowler-Nordheim (“FN”) tunneling through the channel area, and programmed using either channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). To reduce disturbance of the floating gate potential of unselected memory cells during programming operations and read operations, the unselected word lines are brought to a negative potential rather than ground potential. To reduce disturbance of the floating gate potential of unselected memory cells during FN erase operations, the unselected word lines are brought to a positive potential rather than ground potential.

Abstract: A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.

Abstract: A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.

Abstract: A memory array contains memory cells designed to be erased using Fowler-Nordheim (“FN”) tunneling through the channel area, and programmed using either channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). To reduce disturbance of the floating gate potential of unselected memory cells during programming operations and read operations, the unselected word lines are brought to a negative potential rather than ground potential. To reduce disturbance of the floating gate potential of unselected memory cells during FN erase operations, the unselected word lines are brought to a positive potential rather than ground potential.

Abstract: A memory array contains memory cells designed to be erased using Fowler-Nordheim (“FN”) tunneling through the channel area, and programmed using either channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). To reduce disturbance of the floating gate potential of unselected memory cells during programming operations and read operations, the unselected word lines are brought to a negative potential rather than ground potential. To reduce disturbance of the floating gate potential of unselected memory cells during FN erase operations, the unselected word lines are brought to a positive potential rather than ground potential.

Abstract: A memory device is disclosed that employs hot electron injection for programming operations and Fowler-Nordheim tunneling for erase operations. The memory device requires only a single 5 volt power supply and does not require an external high voltage supply for program or erase operations. The memory device includes a charge pump section that internally generates the high voltage required for programming and erase operations. The same charge pump section is used for both program and erase power requirements.

Abstract: Disclosed is a EEPROM flash memory array utilizing single transistor cells to provide read/write nonvolatile storage. The array includes a plurality of sectors, each oriented along the word line direction, and the sectors may include one or more word lines. An erase select transistor is provided for each sector and each word line includes a pass gate transistor which assists in both the programming and the erase operations.

Abstract: Disclosed is a stacked gate electrically erasable programmable read only memory EEPROM cell which utilizes a floating region and a common pass transistor to provide a cell which is programmable at a relatively low drain voltage and which, in addition, by utilizing a pass transistor, overcomes the programming disturbance and false read problems associated with typical stacked gate memory cells. The cell is constructed such that programming and erasing functions take place at separate locations in the gate oxide. An EEPROM memory cell array, utilizing the above memory cell, is disclosed which provides the ability to achieve both byte erase and block erase as well as byte write capability. Also disclosed is a process for producing such a memory cell and memory array.

Abstract: Disclosed is a nonvolatile memory cell which utilizes a tunnel window to discharge the floating gate at a location spacially displaced from the program path for the cell. Also disclosed is a process for making such a memory cell.

Abstract: A process is disclosed for producing a high density split gate nonvolatile memory cell which includes a floating gate and a control gate that is formed above the floating gate. The drain region is self-aligned to the floating gate and the source region is self-aligned to the control gate. Fully self-aligned implantation is made possible by the process and structure using self-aligned etch. Programming of the memory cell uses standard EPROM programming, and erasing is accomplished by Fowler-Nordheim tunneling or photoemission. The memory cell can be made with a reduced cell size and read current uniformity is obtained.