Abstract: A dual-head, pulseless peristaltic-type pump comprises a pump housing, cover, two compressible tube chambers and two sets of rotatable occluding members. An off-center drive axis driven by motor or other rotational mechanism rotate inner large diameter disk. Balls or rollers between inner disk rotate in one direction from center drive axis where the outer ring is stationary and occludes the tube by linear motion without friction between tube and outer ring. The linear roller occluding motion transfers liquid or slurry from inlet to outlet of tube. In one embodiment, two separate sets of occluding members are installed 180 degree opposite to each other such that pulsations are compensated for and canceled out.

Abstract: A dual-head, pulseless peristaltic-type pump comprises a pump housing, cover, two compressible tube chambers and two sets of rotatable occluding members. An off-center drive axis driven by motor or other rotational mechanism rotate inner large diameter disk. Balls or rollers between inner disk rotate in one direction from center drive axis where the outer ring is stationary and occludes the tube by linear motion without friction between tube and outer ring. The linear roller occluding motion transfers liquid or slurry from inlet to outlet of tube. In one embodiment, two separate sets of occluding members are installed 180 degree opposite to each other such that pulsations are compensated for and canceled out.

Abstract: A content addressable memory (CAM) with built-in power saving management. The CAM includes a comparator circuit region that is coupled to a match line (ML) as well as a swing line (SL). The comparator circuit region is coupled to CAM cells. The comparator region is adapted for comparing match data with stored data within the CAM cells. The ML has its ML voltage level pre-charged to a pre-charge voltage level (Vc). Additionally, the SL is pre-charged to ground. In turn, in response to a data mismatch detected by the comparator, the ML voltage level drops from Vc by a ML voltage swing (Vswing) while the SL charge shares with the Ml. Advantageously, in response to this data mismatch, the SL charge shares with the ML such that Vswing is approximately less or equal to Vc/2. That is, the charge sharing prevents the ML from discharging all the way to ground.

Abstract: A wordline wakeup circuit for use in a static memory responsive to an external clock signal and chip enable signals provided by a controller/microprocessor to perform a memory operation on the static memory. The wordline wakeup circuit receives a global clock (GCLK) signal generated by memory control circuitry from the external clock signal and a word line enable (WLEN) signal asserted by the control circuitry when the chip enables indicate a pending memory operation. The wordline wakeup circuit asserts a wordline wakeup signal (LWLEN) signal as soon as possible after the GCLK signal goes high. The LWLEN signal when asserted activates decoder circuity to assert wordlines as necessary to perform the memory operation. If the WLEN signal is provided, the wordline wakeup circuit keeps the LWLEN signal high for at least the high portion of the GCLK signal, enabling the decoder to execute the memory operation, if the WLEN signal is not provided, the wordline wakeup circuit drops the LWLEN signal.

Abstract: An output buffer (30) is connected to an output signal line and receives an internal power supply voltage, for example 3.3 volts, which is lower than a voltage, for example 5 volts, that other devices which may be connected to the output signal line are able to drive. To protect an output transistor (71) from the harmful effects of the higher voltages on the output signal line, the output buffer (30) includes a special bulk biasing circuit (80). The bulk biasing circuit (80) biases the bulk of the output transistor (71) at an internal power supply voltage when the output buffer is driving and when not driving to a voltage determined by the output signal. To prevent overlap currents, the output buffer (30) includes a special gate biasing circuit (100), which momentarily drives the gate of the output transistor (71) to a voltage equal to the internal power supply voltage when the output buffer (30) stops driving.