Patents by Inventor Steve M. Wilkinson

Steve M. Wilkinson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Designing a printed circuit board (PCB) to detect slivers of conductive material included within vias of the PCB
    Patent number: 11570908
    Abstract: A method may include obtaining a printed circuit board (PCB) that includes a set of vias that include a set of stub regions. The PCB may include a set of layers perpendicular to the set of vias. The set of layers may include a signal layer and a ground layer. The ground layer may be located between the set of stub regions and the signal layer. The method may include drilling to remove at least a portion of a stub region of a via of the set of vias. The method may include performing an electrical test to determine whether a sliver of conductive material is included within the via after drilling to remove the at least a portion of the stub region of the via.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: January 31, 2023
    Assignee: Juniper Networks, Inc.
    Inventors: Steve M. Wilkinson, Daniel J. Prezioso
  • Apparatus, system, and method for mitigating the swiss cheese effect in high-current circuit boards
    Patent number: 11412610
    Abstract: A disclosed apparatus may be a circuit board that includes (1) a first unique sublaminate that includes a plurality of ground layers and a plurality of signal layers, (2) a second unique sublaminate that includes a plurality of power layers and another plurality of signal layers, and (3) a symmetry axis that bisects the circuit board between the first unique sublaminate and the second unique sublaminate, wherein the first unique sublaminate and the second unique sublaminate are distinct from one another. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: August 9, 2022
    Assignee: Juniper Networks, Inc
    Inventors: Boris Reynov, David K. Owen, Michael Clifford Freda, Steve M. Wilkinson, Jing Zhang
  • APPARATUS, SYSTEM, AND METHOD FOR MITIGATING THE SWISS CHEESE EFFECT IN HIGH-CURRENT CIRCUIT BOARDS
    Publication number: 20220141952
    Abstract: A disclosed apparatus may be a circuit board that includes (1) a first unique sublaminate that includes a plurality of ground layers and a plurality of signal layers, (2) a second unique sublaminate that includes a plurality of power layers and another plurality of signal layers, and (3) a symmetry axis that bisects the circuit board between the first unique sublaminate and the second unique sublaminate, wherein the first unique sublaminate and the second unique sublaminate are distinct from one another. Various other apparatuses, systems, and methods are also disclosed.
    Type: Application
    Filed: November 4, 2020
    Publication date: May 5, 2022
    Inventors: Boris Reynov, David K. Owen, Michael Clifford Freda, Steve M. Wilkinson, Jing Zhang
  • DESIGNING A PRINTED CIRCUIT BOARD (PCB) TO DETECT SLIVERS OF CONDUCTIVE MATERIAL INCLUDED WITHIN VIAS OF THE PCB
    Publication number: 20210153359
    Abstract: A method may include obtaining a printed circuit board (PCB) that includes a set of vias that include a set of stub regions. The PCB may include a set of layers perpendicular to the set of vias. The set of layers may include a signal layer and a ground layer. The ground layer may be located between the set of stub regions and the signal layer. The method may include drilling to remove at least a portion of a stub region of a via of the set of vias. The method may include performing an electrical test to determine whether a sliver of conductive material is included within the via after drilling to remove the at least a portion of the stub region of the via.
    Type: Application
    Filed: January 29, 2021
    Publication date: May 20, 2021
    Inventors: Steve M. WILKINSON, Daniel J. PREZIOSO
  • Designing a printed circuit board (PCB) to detect slivers of conductive material included within vias of the PCB
    Patent number: 10917976
    Abstract: A method may include obtaining a printed circuit board (PCB) that includes a set of vias that include a set of stub regions. The PCB may include a set of layers perpendicular to the set of vias. The set of layers may include a signal layer and a ground layer. The ground layer may be located between the set of stub regions and the signal layer. The method may include drilling to remove at least a portion of a stub region of a via of the set of vias. The method may include performing an electrical test to determine whether a sliver of conductive material is included within the via after drilling to remove the at least a portion of the stub region of the via.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: February 9, 2021
    Assignee: Juniper Networks, Inc.
    Inventors: Steve M. Wilkinson, Daniel J. Prezioso