Patents by Inventor Steve McCormack

Steve McCormack has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7635621
    Abstract: A lateral double-diffused metal oxide semiconductor (LDMOS) device is disclosed. The LDMOS device comprises a gate region and a body region under the gate region. The LDMOS device includes an enhanced drift region under the gate region. The enhanced drift region touches the body region. By designing the device such that the enhanced drift region overlaps and compensates the lateral tail of the body region of the LDMOS transistor, the Ron*area product is reduced. Accordingly, the on-resistance is significantly reduced while minimally affecting the breakdown voltage of the device.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: December 22, 2009
    Assignee: Micrel, Inc.
    Inventors: Steve McCormack, Ji-hyoung Yoo
  • Publication number: 20070246771
    Abstract: A lateral double-diffused metal oxide semiconductor (LDMOS) device is disclosed. The LDMOS device comprises a gate region and a body region under the gate region. The LDMOS device includes an enhanced drift region under the gate region. The enhanced drift region touches the body region. By designing the device such that the enhanced drift region overlaps and compensates the lateral tail of the body region of the LDMOS transistor, the Ron*area product is reduced. Accordingly, the on-resistance is significantly reduced while minimally affecting the breakdown voltage of the device.
    Type: Application
    Filed: April 25, 2006
    Publication date: October 25, 2007
    Inventors: Steve McCormack, Ji-hyoung Yoo
  • Publication number: 20060065891
    Abstract: A zener zap device is formed in a fabrication process using a tungsten plug process having standard sized contact openings. The zener zap device includes first and second regions of opposite conductivity types formed in a semiconductor layer. A dielectric layer overlaying the surface of the semiconductor layer includes first and second contact openings positioned above and exposing a portion of the first and second regions respectively. The first contact opening is an enlarged contact opening having dimensions larger than the standard sized contact opening. A first metal contact formed in the first enlarged contact opening includes tungsten sidewall and aluminum formed in electrical contact with the exposed surface of the first region. In one embodiment, the second contact opening is also an enlarged contact opening for forming a second metal contact having tungsten sidewall and aluminum in electrical contact with the exposed surface of the second region.
    Type: Application
    Filed: September 30, 2004
    Publication date: March 30, 2006
    Inventors: Steve McCormack, Ji-hyoung Yoo, Dennis Rossman, Kevin Brown
  • Patent number: 6838350
    Abstract: A method for fabricating a bipolar transistor includes forming a first region of a first conductivity type in a semiconductor structure to form a collector region and forming a second region of a second conductivity type in the first region to form a base region. A first mask is applied including an opening defining an emitter region of the bipolar transistor. The method further includes a triple implantation process using the first mask. Thus, a third region of the first conductivity type is formed in the first region and overlaid the second region. A fourth region of the second conductivity type is formed in the second region and is more heavily doped than the second region. A fifth region of the first conductivity type is formed in the second region and above the fourth region. The fifth region forms the emitter region of the bipolar transistor.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: January 4, 2005
    Assignee: Micrel, Inc.
    Inventors: Martin E. Garnett, Peter Zhang, Steve McCormack, Ji-hyoung Yoo
  • Publication number: 20040212043
    Abstract: A method for fabricating a bipolar transistor includes forming a first region of a first conductivity type in a semiconductor structure to form a collector region and forming a second region of a second conductivity type in the first region to form a base region. A first mask is applied including an opening defining an emitter region of the bipolar transistor. The method further includes a triple implantation process using the first mask. Thus, a third region of the first conductivity type is formed in the first region and overlaid the second region. A fourth region of the second conductivity type is formed in the second region and is more heavily doped than the second region. A fifth region of the first conductivity type is formed in the second region and above the fourth region. The fifth region forms the emitter region of the bipolar transistor.
    Type: Application
    Filed: April 25, 2003
    Publication date: October 28, 2004
    Inventors: Martin E. Garnett, Peter Zhang, Steve McCormack, Ji-hyoung Yoo