Patents by Inventor Steve Merchant

Steve Merchant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reliable high-voltage junction field effect transistor and method of manufacturing therefor
    Patent number: 7704813
    Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: April 27, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Kaiyuan Chen, Joe Trogolo, Tathagata Chatterjee, Steve Merchant
  • Reliable High-Voltage Junction Field Effect Transistor and Method of Manufacturing Therefor
    Publication number: 20080090346
    Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).
    Type: Application
    Filed: November 1, 2007
    Publication date: April 17, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Kaiyuan Chen, Joe Trogolo, Tathagata Chatterjee, Steve Merchant
  • Reliable high-voltage junction field effect transistor and method of manufacture therefor
    Patent number: 7312481
    Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: December 25, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Kaiyuan Chen, Joe Trogolo, Tathagata Chatterjee, Steve Merchant
  • Reliable high-voltage junction field effect transistor and method of manufacture therefor
    Publication number: 20060071247
    Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).
    Type: Application
    Filed: October 1, 2004
    Publication date: April 6, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Kaiyuan Chen, Joe Trogolo, Tathagata Chatterjee, Steve Merchant