Abstract: An ultra shallow junction (USJ) FET device and method for forming the same with improved control over SDE or LDD doped region interfaces to improve device performance and reliability is provided, the method including providing a semiconductor substrate; forming a gate structure comprising a gate dielectric, an overlying gate electrode, and first offset spacers adjacent either side of the gate electrode; forming at least one doped semiconductor layer comprising dopants over a respective source and drain region adjacent the respective first offset spacers; forming second offset spacers adjacent the respective first offset spacers; and, thermally treating the at least one semiconductor layer to cause out-diffusion of the dopants to form doped regions in the semiconductor substrate.

Abstract: A method is disclosed for forming silicided gate electrodes and unsilicided poly resistors. After patterning a semiconductor material for the gate electrode and resistor structures, a first dielectric layer is used to protect a poly resistor that is not to be silicided, then a first silicidation is performed for partially siliciding the gate electrode of the transistor. If the gate electrode is thick, a second dielectric layer is used to protect the resistor that is not to be silicided, then a second silicidation is performed for fully siliciding the gate electrode.

Abstract: A method is disclosed for forming silicided gate electrodes and unsilicided poly resistors. After patterning a semiconductor material for the gate electrode and resistor structures, a first dielectric layer is used to protect a poly resistor that is not to be silicided, then a first silicidation is performed for partially siliciding the gate electrode of the transistor. If the gate electrode is thick, a second dielectric layer is used to protect the resistor that is not to be silicided, then a second silicidation is performed for fully siliciding the gate electrode.

Abstract: Provided is a method of manufacturing a microelectronic device. In one example where the device includes a semiconductor substrate with a gate feature and a shallow junction, the method includes introducing dopants to the substrate to form a source region and a drain region. A strained layer may be formed over the substrate after introducing the dopants, and an annealing process may be performed after forming the strained layer.

Abstract: A method of forming a raised source/drain proximate a spacer of a gate of a transistor on a substrate, and a semiconductor device of an integrated circuit employing the same. In one embodiment, the method includes orienting the gate substantially along a <100> direction of the substrate. The method also includes providing a semiconductor material adjacent the spacer of the gate to form a raised source/drain layer of the raised source/drain oriented substantially along a <100> direction of the substrate.