Patents by Inventor Steve Pawlowski

Steve Pawlowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240104338
    Abstract: A method comprising: sampling a temporal causal graph from a temporal graph distribution specifying probabilities of directed causal edges between different variables of a feature vector at a present time step, and from one variable at a preceding time step to another variables at the present time step. Based on this there are identified: a present parent which is a cause of the selected variable in the present time step, and a preceding parent which is a cause of the selected variable from the preceding time step. The method then comprises: inputting a value of each identified present and preceding parent into a respective encoder, resulting in a respective embedding of each of the present and preceding parents; combining the embeddings of the present and preceding parents, resulting in a combined embedding; inputting the combined embedding into a decoder, resulting in a reconstructed value of the selected variable.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Inventors: Wenbo GONG, Cheng ZHANG, Nick PAWLOWSKI, Joel JENNINGS, Karen FASSIO, Marife DEFANTE, Steve THOMAS, Alice HORAN, Chao MA, Matthew ASHMAN, Agrin HILMKIL
  • Publication number: 20230229556
    Abstract: There are provided methods and systems for improving RAS features of a memory device. For example, there is provided a system that includes a memory and a memory side cache. The system further includes a processor that is configured to minimize accesses to the memory by executing certain operations. The operations can include computing a new parity based on old data, new data, and an old parity in response to data from the memory side cache being written to the memory.
    Type: Application
    Filed: August 26, 2022
    Publication date: July 20, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Patrick Estep, Steve Pawlowski, Emanuele Confalonieri, Nicola Del Gatto, Paolo Amato
  • Patent number: 7231486
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: June 12, 2007
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, David Harriman, Randolph L. Campbell, Jose A. Vargas, Clifford D. Hall, Prashant Sethi, Steve Pawlowski
  • Publication number: 20030115380
    Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.
    Type: Application
    Filed: August 23, 2002
    Publication date: June 19, 2003
    Inventors: Jasmin Ajanovic, David Harriman, Randolph L. Campbell, Jose A. Vargas, Clifford D. Hall, Prashant Sethi, Steve Pawlowski
  • Patent number: 6148356
    Abstract: A computer system includes a host processor coupled to a host bus. A bridge controller is coupled to the host bus and to a plurality of first buses. The computer system also includes one or more bus bridges, each coupled to the bridge controller via one or more of said first buses. Each bus bridge is connected to one or more second buses. Either the first buses or the second buses are each configurable in either an independent mode in which the bus operates independently, or a combined mode in which two or more of said first buses or said second buses are combined to create a single bus.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: November 14, 2000
    Assignee: Intel Corporation
    Inventors: David W. Archer, D. Michael Bell, Doug Moran, Steve Pawlowski