Patents by Inventor Steve PRINS

Steve PRINS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SRAM WELL-TIE WITH AN UNINTERRUPTED GRATED FIRST POLY AND FIRST CONTACT PATTERNS IN A BIT CELL ARRAY
    Publication number: 20160049410
    Abstract: An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as gates and contacts, which have alternating line and space configurations in SRAM cells. Strap rows of the SRAM containing well ties and/or substrate taps which have SRAM cells on two opposite sides are configured so that the alternating line and space configurations are continuous across the regions containing the well ties and substrate taps.
    Type: Application
    Filed: October 28, 2015
    Publication date: February 18, 2016
    Inventors: Anand SESHADRI, Steve PRINS, Russell MCMULLAN
  • CONTEXT PROTECTION FOR A COLUMN INTERLEAVED MEMORY
    Publication number: 20150029773
    Abstract: A semiconductor memory cell includes a set of circuit structures, each having column input/output circuits. The semiconductor memory cell further includes a set of replicas corresponding to the column input/output circuits. The set of replicas are non-functional and fills an empty space next to the column input/output circuits and hence, provides context protection for the column input/output circuits.
    Type: Application
    Filed: July 23, 2013
    Publication date: January 29, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Lakshmikantha Holla, Thomas ATON, Steve PRINS, Dharaneedharan S.
  • SRAM WELL-TIE WITH AN UNINTERRUPTED GRATED FIRST POLY AND FIRST CONTACT PATTERNS IN A BIT CELL ARRAY
    Publication number: 20140327082
    Abstract: An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as gates and contacts, which have alternating line and space configurations in SRAM cells. Strap rows of the SRAM containing well ties and/or substrate taps which have SRAM cells on two opposite sides are configured so that the alternating line and space configurations are continuous across the regions containing the well ties and substrate taps.
    Type: Application
    Filed: May 1, 2013
    Publication date: November 6, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Anand SESHADRI, Steve PRINS, Russell MCMULLAN