Abstract: A packet and inspection system for monitoring the performance of one or more flows on a packet network comprises a processor and memory coupled to each other and to a network bus. The memory stores instructions to be executed by the processor and data to be modified by the execution of the instructions. A processor-controlled arbiter is coupled with the processor and the network bus, and upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, the arbiter requests execution by the processor of selected instructions stored in the memory by providing the processor with the address of the selected instructions in the memory. The memory provides the processor with data associated with the selected instructions, and the processor modifies the data upon execution of the selected instructions.

Abstract: A method for transmitting a packet on a logical port comprising two or more physical ports comprises receiving a packet of a class of service; storing the packet in a memory; maintaining a lookup table relating a plurality of identifiers to at least one physical port; storing a pointer to the stored packet in the memory in a single pointer list for the class of service along with a selected one of the identifiers; and copying the stored packet to one or more physical ports corresponding to the selected identifier for transmission on at least one of the physical ports. In one implementation, a plurality of the physical ports are grouped into a logical port, and the received packet is processed to determine its logical port and its class of service.

Abstract: A method of simplifying the implementation of Synchronous Ethernet on an Ethernet device having a first port and a second port device using a predetermined protocol and signaling, comprises delivering a master clock from a Synchronous Ethernet system to the first port of the Ethernet device; transmitting the delivered master clock to the second port of the Ethernet device independently of the protocol and signaling of the Ethernet device; and transmitting the master clock from the second port of the Ethernet device to a downstream device that supports Synchronous Ethernet. In one implementation, the Ethernet device has a local clock, and the method synchronizes the local clock to the master clock. In another implementation, the Ethernet device does not have a local clock, and the master clock is transmitted from the second port of the Ethernet device to the downstream device without any synchronizing operation at the Ethernet device.

Abstract: A packet generation and inspection system for monitoring the performance of one or more flows on a packet network comprises a processor and memory coupled to each other and to a network bus. The memory stores instructions to be executed by the processor and data to be modified by the execution of the instructions. A processor-controlled arbiter is coupled with the processor and the network bus, and upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, the arbiter requests execution by the processor of selected instructions stored in the memory by providing the processor with the address of the selected instructions in the memory. The memory provides the processor with data associated with the selected instructions, and the processor modifies the data upon execution of the selected instructions.

Abstract: A system for testing Ethernet paths or links without adversely impacting non-test traffic. The system includes a test traffic generator that includes a scheduler that determines when a new test packet is generated. The test traffic generator includes a packet creator that builds a test packet and a transmitter for transmitting the test packet via the Ethernet path or link. The packet creator sends the test packet to the transmitter. The traffic generator includes a transmit credit block coupled to the transmitter or to the scheduler. The transmit credit block stores an amount of credits representing a number of bytes that are available to transmit and decrements the amount each time a non-test packet is communicated via the Ethernet path or link.

Abstract: A system for testing Ethernet paths or links without adversely impacting non-test traffic. The system includes a test traffic generator that includes a scheduler that determines when a new test packet is generated. The test traffic generator includes a packet creator that builds a test packet and a transmitter for transmitting the test packet via the Ethernet path or link. The packet creator sends the test packet to the transmitter. The traffic generator includes a transmit credit block coupled to the transmitter or to the scheduler. The transmit credit block stores an amount of credits representing a number of bytes that are available to transmit and decrements the amount each time a non-test packet is communicated via the Ethernet path or link.

Abstract: A system for negotiating Ethernet link settings between interconnected nodes in a network having an Ethernet protocol stack that includes a PCS sub-layer with an auto-negotiation function. The system comprises connecting an intermediate device coupled between two network nodes via optical or copper interfaces, with the link settings between each node and the connected intermediate device being the same, thereby bypassing the auto-negotiation of the PCS sub-layer in the intermediate device. The intermediate device may transparently send negotiation messages from each node to the other during the link negotiation phase without interacting with those messages. Instead of the intermediate device, a single form pluggable (SFP) device may be connected between the two network nodes via optical or copper interfaces on the network side and via an SFP slot on the device side.

Abstract: A system for efficient routing of an OAM) frame in an Ethernet switch receives an OAM frame at a first port; building a first classification key dependent on an OAM frame header; classifies in a context of the first port to create a first classification; resolves action dependent on the first classification; modifies the first classification key to create a second classification key; classifies the frame in a context of the second port to create a second classification; sends the second classification key to an OAM engine coupled to the Ethernet switch for modification into a third classification key; receives the third classification key from the OAM engine; modifies the third classification key into a final classification key; modifies the header of the OAM frame with the final classification key; and sends the modified OAM frame to a switching fabric of the Ethernet switch.

Abstract: A system for negotiating Ethernet link settings between interconnected nodes in a network having an Ethernet protocol stack that includes a PCS sub-layer with an auto-negotiation function. The system comprises connecting an intermediate device coupled between two network nodes via optical or copper interfaces, with the link settings between each node and the connected intermediate device being the same, thereby bypassing the auto-negotiation of the PCS sub-layer in the intermediate device. The intermediate device may transparently send negotiation messages from each node to the other during the link negotiation phase without interacting with those messages. Instead of the intermediate device, a single form pluggable (SFP) device may be connected between the two network nodes via optical or copper interfaces on the network side and via an SFP slot on the device side.

Abstract: A system for efficient routing of an OAM) frame in an Ethernet switch receives an OAM frame at a first port; building a first classification key dependent on an OAM frame header; classifies in a context of the first port to create a first classification; resolves action dependent on the first classification; modifies the first classification key to create a second classification key; classifies the frame in a context of the second port to create a second classification; sends the second classification key to an OAM engine coupled to the Ethernet switch for modification into a third classification key; receives the third classification key from the OAM engine; modifies the third classification key into a final classification key; modifies the header of the OAM frame with the final classification key; and sends the modified OAM frame to a switching fabric of the Ethernet switch.

Abstract: In one embodiment, a connection is maintained between a pair of ethernet ports that have circuitry connected in series with the ports and receiving power-over-ethernet (PoE) from one of the ports, by providing a controllable bypass circuit coupled to the pair of ethernet ports in parallel with the circuitry receiving power-over-ethernet, sensing a preselected condition, and opening and closing the bypass circuit in response to the presence or absence of the preselected condition. Power sourcing equipment (PSE) may supply the one of the ports with power over ethernet, and the circuitry may transports data between the pair of ethernet ports. The circuitry may also supply the switch with a control signal in response to the detection of the preselected condition.

Abstract: A method of simplifying the implementation of Synchronous Ethernet on an Ethernet device having a first port and a second port device using a predetermined protocol and signaling, comprises delivering a master clock from a Synchronous Ethernet system to the first port of the Ethernet device; transmitting the delivered master clock to the second port of the Ethernet device independently of the protocol and signaling of the Ethernet device; and transmitting the master clock from the second port of the Ethernet device to a downstream device that supports Synchronous Ethernet. In one implementation, the Ethernet device has a local clock, and the method synchronizes the local clock to the master clock. In another implementation, the Ethernet device does not have a local clock, and the master clock is transmitted from the second port of the Ethernet device to the downstream device without any synchronizing operation at the Ethernet device.

Abstract: A method of simplifying the implementation of Synchronous Ethernet on an Ethernet device having a first port and a second port device using a predetermined protocol and signaling, comprises delivering a master clock from a Synchronous Ethernet system to the first port of the Ethernet device; transmitting the delivered master clock to the second port of the Ethernet device independently of the protocol and signaling of the Ethernet device; and transmitting the master clock from the second port of the Ethernet device to a downstream device that supports Synchronous Ethernet. In one implementation, the Ethernet device has a local clock, and the method synchronizes the local clock to the master clock. In another implementation, the Ethernet device does not have a local clock, and the master clock is transmitted from the second port of the Ethernet device to the downstream device without any synchronizing operation at the Ethernet device.

Abstract: A system for testing Ethernet paths or links without adversely impacting non-test traffic. The system includes a test traffic generator that includes a scheduler that determines when a new test packet is generated. The test traffic generator includes a packet creator that builds a test packet and a transmitter for transmitting the test packet via the Ethernet path or link. The packet creator sends the test packet to the transmitter. The traffic generator includes a transmit credit block coupled to the transmitter or to the scheduler. The transmit credit block stores an amount of credits representing a number of bytes that are available to transmit and decrements the amount each time a non-test packet is communicated via the Ethernet path or link.

Abstract: A method of providing information regarding an Ethernet frame, within the Ethernet preamble of the Ethernet frame, comprises inserting into the Ethernet preamble an inter-line-card header that includes a start control character, a version number, a parity bit, a source port, a destination port, and a forwarding domain entry; and preserving said inter-line-card header, inside of said Ethernet preamble, in a Media Access Control (MAC) sub-layer in said Ethernet frame. The method may include a step of selecting the decoding format for the inter-line-card header corresponding to the version number and/or forwarding other Ethernet frames according to additional forwarding information provided by the forwarding domain entry. The inter-line-card header may be preserved in the MAC sub-layer by keeping the Ethernet preamble at the beginning of an Ethernet frame received over an Ethernet backplane, and passing the combined preamble and associated Ethernet frame to an inter-line-card header processing module.

Abstract: A system for testing Ethernet paths or links without adversely impacting non-test traffic. The system includes a test traffic generator that includes a scheduler that determines when a new test packet is generated. The test traffic generator includes a packet creator that builds a test packet and a transmitter for transmitting the test packet via the Ethernet path or link. The packet creator sends the test packet to the transmitter. The traffic generator includes a transmit credit block coupled to the transmitter or to the scheduler. The transmit credit block stores an amount of credits representing a number of bytes that are available to transmit and decrements the amount each time a non-test packet is communicated via the Ethernet path or link.

Abstract: A packet generation and inspection system for monitoring the performance of one or more flows on a packet network comprises a processor and memory coupled to each other and to a network bus. The memory stores instructions to be executed by the processor and data to be modified by the execution of the instructions. A processor-controlled arbiter is coupled with the processor and the network bus, and upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, the arbiter requests execution by the processor of selected instructions stored in the memory by providing the processor with the address of the selected instructions in the memory. The memory provides the processor with data associated with the selected instructions, and the processor modifies the data upon execution of the selected instructions.

Abstract: A packet generation and inspection system for monitoring the performance of one or more flows on a packet network comprises a processor and memory coupled to each other and to a network bus. The memory stores instructions to be executed by the processor and data to be modified by the execution of the instructions. A processor-controlled arbiter is coupled with the processor and the network bus, and upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, the arbiter requests execution by the processor of selected instructions stored in the memory by providing the processor with the address of the selected instructions in the memory. The memory provides the processor with data associated with the selected instructions, and the processor modifies the data upon execution of the selected instructions.

Abstract: A method for accurately measuring one or more network performance statistics during one or more sampling periods comprises processing a received data packet to identify flow information and time of arrival; transmitting the data packet, along with metadata comprising the flow information and the time of arrival, to a sample processing module; replaying the reception of the data packet based on the relative speed of the transmission link and the databus and the time of arrival; incrementing a number of bytes received for the data packet for a first sampling period; starting a second sampling period at a predetermined time and incrementing a number of bytes received for the data packet for the second sampling period, if the replaying is not completed. The number of bytes received for the data packet for the first and second sampling periods are processed into first and second sampling period statistics, respectively.

Abstract: A method for accurately measuring one or more network performance statistics during one or more sampling periods comprises processing a received data packet to identify flow information and time of arrival; transmitting the data packet, along with metadata comprising the flow information and the time of arrival, to a sample processing module; replaying the reception of the data packet based on the relative speed of the transmission link and the databus and the time of arrival; incrementing a number of bytes received for the data packet for a first sampling period; starting a second sampling period at a predetermined time and incrementing a number of bytes received for the data packet for the second sampling period, if the replaying is not completed. The number of bytes received for the data packet for the first and second sampling periods are processed into first and second sampling period statistics, respectively.