Abstract: A retaining clip is provided for use with a heat sink. The heat sink has a flat bottom surface in heat conducting engagement with an electronic device and fins extending from a top surface of the heat sink, the fins defining a channel. The retainer clip includes a middle section and a first end section and a second end section on either side of the middle section. The middle section fits within the channel and engages the heat sink to hold the bottom surface against the electronic device. The middle section further includes a portion extending above the top surface, within the channel, to limit rotation of the heat sink. Each of the first and second end sections include a pivot end adjacent to the middle section, a distal end to engage an anchor, a first leg adjacent to the distal end, a second leg adjacent to a pivot end, and a bend between the first leg and the second leg, the bend located to form a moment arm from the pivot end.

Abstract: A retaining clip is provided for use with a heat sink. The heat sink has a flat bottom surface in heat conducting engagement with an electronic device and fins extending from a top surface of the heat sink, the fins defining a channel. The retainer clip includes a middle section and a first end section and a second end section on either side of the middle section. The middle section fits within the channel and engages the heat sink to hold the bottom surface against the electronic device. The middle section further includes a portion extending above the top surface, within the channel, to limit rotation of the heat sink. Each of the first and second end sections include a pivot end adjacent to the middle section, a distal end to engage an anchor, a first leg adjacent to the distal end, a second leg adjacent to a pivot end, and a bend between the first leg and the second leg, the bend located to form a moment arm from the pivot end.

Abstract: A computer-implemented method, to facilitate processing a payment for an online transaction, includes, responsive to receiving secure transaction data from a merchant server, using a payment processor to generate a transaction data identifier to identify the transaction data. The payment processor communicates the transaction data identifier to the merchant server. In response to receiving a request to process a payment, including the transaction data identifier, the payment processor requests user credentials from a user. Upon receiving user credentials from the user, the payment processor verifies the user credentials. The payment processor processes the payment and generates a payment identifier to identify payment data associated with the payment. The payment processor communicates the payment identifier to the merchant server.

Abstract: A computer-implemented method, to facilitate processing a payment for an online transaction, includes, responsive to receiving secure transaction data from a merchant server, using a payment processor to generate a transaction data identifier to identify the transaction data. The payment processor communicates the transaction data identifier to the merchant server. In response to receiving a request to process a payment, including the transaction data identifier, the payment processor requests user credentials from a user. Upon receiving user credentials from the user, the payment processor verifies the user credentials. The payment processor processes the payment and generates a payment identifier to identify payment data associated with the payment. The payment processor communicates the payment identifier to the merchant server.

Abstract: System and method are proposed for intelligent assignment of submitted information processing jobs to computing resources in an information processing grid based upon real-time measurements of job behavior and predictive analysis of job throughput and computing resource consumption of the correspondingly generated workloads. The job throughput and computing resource utilization are measured and analyzed in multiple parametric dimensions. The analyzed workload may work with a job scheduling system to provide optimized job dispatchment to computing resources across the grid. Application of a parametric weighting system to the parametric dimensions makes the optimization system dynamic and flexible. Through adjustment of these parametric weights, the focus of the optimization can be adjusted dynamically to support the immediate operational goals of the system as a whole.

Abstract: A scalable Internet engine is comprised of a large number of commercially available server boards each arranged as an engine blade in a power and space efficient cabinet. The engine blades are removably positioned in a front side of the cabinet in a vertical orientation. A through-plane in the middle of a chassis assembly within the cabinet provides common power and control peripheral signals to all engine blades. I/O signals for each engine blade are routed through apertures in the through-plane to interface cards positioned in the rear of the cabinet. The scalable engine can accommodate different types of server boards in the same chassis assembly because of a common blade carrier structure. Different types of commercially available motherboards are mounted in the common blade carrier structure that provides a uniform mechanical interface to the chassis assembly.

Abstract: A scalable Internet engine is comprised of a large number of commercially available server boards each arranged as an engine blade in a power and space efficient cabinet. The engine blades are removably positioned in a front side of the cabinet in a vertical orientation. A through-plane in the middle of a chassis assembly within the cabinet provides common power and control peripheral signals to all engine blades. I/O signals for each engine blade are routed through apertures in the through-plane to interface cards positioned in the rear of the cabinet. The scalable engine can accommodate different types of server boards in the same chassis assembly because of a common blade carrier structure. Different types of commercially available motherboards are mounted in the common blade carrier structure that provides a uniform mechanical interface to the chassis assembly.

Abstract: A scalable Internet engine is comprised of a large number of commercially available server boards each arranged as an engine blade in a power and space efficient cabinet. The engine blades are removably positioned in a front side of the cabinet in a vertical orientation. A through plane in the middle of a chassis assembly within the cabinet provides common power and control peripheral signals to all engine blades. I/O signals for each engine blade are routed through apertures in the through plane to interface cards positioned in the rear of the cabinet. The scalable engine can accommodate different types of server boards in the same chassis assembly because of a common blade carrier structure. Different types of commercially available motherboards are mounted in the common blade carrier structure that provides a uniform mechanical interface to the chassis assembly.

Abstract: An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.

Abstract: A rack-mount data server includes a housing, a plurality of data server components supported by the housing, the components including at least one peripheral storage device, a logic chassis for the data server, at least one disk drive on which the data server stores files, and at least one power supply, and a plurality of racks coupled with the housing to accommodate the data server components, the racks including a first topmost rack accommodating the at least one peripheral storage device and a second rack accommodating the logic chassis, the housing supporting the second rack underneath the first rack as the second topmost rack. The data server also includes a front door and a top door, the top door and the front door being interlockable with each other such that when the top door and the front door are in their closed positions, one of the top door and the front door locks the other of the top door and the front door in its closed position.

Abstract: A method of accessing common memory in a cluster architecture for a highly parallel multiprocessor scaler/factor computer system using a plurality of segment registers in which is first determined whether a logical address is within a start and end range as defined by the segment registers and then relocating the logical address to a physical address using a displacement value in another segment register.

Abstract: A unified parallel processing architecture connects together an extendible number of clusters of multiple numbers of processors to create a high performance parallel processing computer system. Multiple processors are grouped together into four or more physically separable clusters, each cluster having a common cluster shared memory that is symmetrically accessible by all of the processors in that cluster; however, only some of the clusters are adjacently interconnected. Clusters are adjacently interconnected to form a floating shared memory if certain memory access conditions relating to relative memory latency and relative data locality can create an effective shared memory parallel programming environment. A shared memory model can be used with programs that can be executed in the cluster shared memory of a single cluster, or in the floating shared memory that is defined across an extended shared memory space comprised of the cluster shared memories of any set of adjacently interconnected clusters.

Abstract: The present invention includes methods and apparatus for creating a packaging architecture for a highly parallel multiprocessor system. The packaging architecture of the present invention can provide for distribution of power, cooling and interconnections at all levels of components in a highly parallel multiprocessor system, while maximizing the number of circuits per unit time within certain operational constraints of such a multiprocessor system.

Abstract: A method and apparatus for non-sequential access to shared resources in a multiple requestor system uses a variety of tags to effectively re-order the data at its destination. In simplest form, the tag directs switching logic to where in a buffer to locate another tag for direction information or where in a buffer or processor (register) to put the response associated with the tag. For example, loading data from memory requires that the requestor provide a request signal, an address, and a request tag. The request signal validates the address and request tag. The address specifies the location of the requested data in memory. The request tag specifies where to put the data when it is returned to the processor.

Abstract: A cluster architecture for a highly parallel multiprocessor computer processing system is comprised of one or more clusters of tightly-coupled, high-speed processors capable of both vector and scalar parallel processing that can symmetrically access shared resources associated with the cluster, as well as the shared resources associated with other clusters.

Abstract: An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.

Abstract: A distributed architecture for the input/output system for a multiprocessor system provides for equal and democratic access to all shared hardware resources by both the processors and the external interface ports of the multiprocessor system. This allows one or more input/output concentrators attached to the external interface ports to have complete access to all of the shared hardware resources across the multiprocessor system without requiring processor intervention. The distributed input/output system provides for communication of data and control information between a set of common shared hardware resources and a set of external data sources. The result is a highly parallel multiprocessor system that has multiple parallel high performance input/output ports capable of operating in a distributed fashion.