Patents by Inventor Steve S. Chung

Steve S. Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9336869
    Abstract: A memory cell and the associated array circuits are disclosed. The memory array circuit includes a plurality of memory units, in which each of the memory units includes a storage device and a field-effect transistor. The storage device includes a top electrode, a bottom electrode and an oxide-based dielectric layer. The top electrode is formed by metal or metallic oxide dielectrics and connected to a word line. The bottom electrode is formed by metal, and the oxide-based dielectric layer is placed between the top electrode and the bottom electrode. The field-effect transistor includes a gate terminal connected to the bottom electrode, a source terminal connected to a ground line, and a drain terminal connected to a bit line. The resistance of the storage device is configured to be adjusted according to a first voltage applied to the word line and a second voltage applied to the bit line.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: May 10, 2016
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Steve S. Chung, E-Ray Hsieh
  • Publication number: 20160027844
    Abstract: A high density NAND-type nonvolatile resistance random access storage circuit and its operations are disclosed herein. A unit memory cell of the circuit includes a field effect transistor (FET) with a resistance changeable component connected to its gate electrode. The field effect transistor is an n-channel field effect transistor or a p-channel field effect transistor. By applying the voltage or current between the top electrode of the resistive random access component and the FET drain or source electrode, more than two stable states can be maintained such that these states can be drawn from the FET drain or source electrode. The NAND circuit includes the above unit cell as a center to form a multi-bit memory. The circuit consists of multi-bit memories connected in series, has a NAND logic gate function, and forms output of this NAND circuit which can be drawn in a form of series output.
    Type: Application
    Filed: July 24, 2015
    Publication date: January 28, 2016
    Inventors: Steve S. CHUNG, E-Ray HSIEH
  • Publication number: 20160027507
    Abstract: A memory cell and the associated array circuits are disclosed. The memory array circuit includes a plurality of memory units, in which each of the memory units includes a storage device and a field-effect transistor. The storage device includes a top electrode, a bottom electrode and an oxide-based dielectric layer. The top electrode is formed by metal or metallic oxide dielectrics and connected to a word line. The bottom electrode is formed by metal, and the oxide-based dielectric layer is placed between the top electrode and the bottom electrode. The field-effect transistor includes a gate terminal connected to the bottom electrode, a source terminal connected to a ground line, and a drain terminal connected to a bit line. The resistance of the storage device is configured to be adjusted according to a first voltage applied to the word line and a second voltage applied to the bit line.
    Type: Application
    Filed: July 27, 2015
    Publication date: January 28, 2016
    Inventors: Steve S. CHUNG, E-Ray HSIEH
  • Publication number: 20120126197
    Abstract: The present invention discloses a structure and process of basic complementary logic gate made by junctionless transistors. Junctionless N-channel transistor(s) and junctionless P-channel transistor(s) are formed on a semiconductor wafer, a conducting contact structure is used to connect the transistors to form a basic complementary logic gate(s) such as inverter, NAND, NOR, etc.
    Type: Application
    Filed: March 9, 2011
    Publication date: May 24, 2012
    Applicant: National Chiao Tung University
    Inventors: Steve S. Chung, E. R. Hsieh
  • Patent number: 6746883
    Abstract: A low leakage charge pumping (CP) method has been implemented for direct determination of interface traps in ultra-short gate length MOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12 Å-16 Å gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has been demonstrated successfully for variousRTNO grown and RPN treated oxide CMOS devices with very thin gate oxide. It can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relation to the interface trap generation. In addition, the current method can be used to determine the physical channel length of CMOS devices.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: June 8, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Steve S. Chung, Shang-Jr Chen, Chien-Kuo Yang, Der-Yuan Wu
  • Publication number: 20030224545
    Abstract: A low leakage charge pumping (CP) method has been implemented for direct determination of interface traps in ultra-short gate length MOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12 Å-16 Å gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has been demonstrated successfully for various RTNO grown and RPN treated oxide CMOS devices with very thin gate oxide. It can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relation to the interface trap generation. In addition, the current method can be used to determine the physical channel length of CMOS devices.
    Type: Application
    Filed: June 4, 2002
    Publication date: December 4, 2003
    Inventors: Steve S. Chung, Shang-Jr Chen, Chien-Kuo Yang, Der-Yuan Wu
  • Patent number: 6507066
    Abstract: A method of forming a Flash EEPROM device with a gate electrode stack includes forming a tunnel oxide layer, a floating gate electrode layer, a dielectric layer, and a control gate layer on a doped silicon semiconductor substrate. Then form source/drain regions in the substrate. Next, form a surface P+ doped halo region in the surface of the N+ source region juxtaposed with the control gate electrode. The P+ halo region is surrounded by the N+ source region. The result is a device which is erased by placing a negative voltage of about −10V on the control gate and a positive voltage of about 5V on the combined source region/halo region to produce accumulation of holes in the channel which distributes the flow of electrons into the channel rather than concentrating the electrons near the interface between the source region and the edge of the tunnel oxide layer. The tunnel oxide layer has a thickness from about 70 Å to about 120 Å.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: January 14, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ching-Hsiang Hsu, Mong-Song Liang, Steve S. Chung
  • Patent number: 6087219
    Abstract: A method of forming a Flash EEPROM device with a gate electrode stack includes forming a a tunnel oxide layer, a floating gate electrode layer, a dielectric layer, and a control gate layer on a doped silicon semiconductor substrate. Then form source/drain regions in the substrate. Next, form a surface P+ doped halo region in the surface of the N+ source region juxtaposed with the control gate electrode. The P+ halo region is surrounded by the N+ source region. The result is a device which is erased by placing a negative voltage of about -10V on the control gate and a positive voltage of about 5V on the combined source region/halo region to produce accumulation of holes in the channel which distributes the flow of electrons into the channel rather than concentrating the electrons near the interface between the source region and the edge of the tunnel oxide layer. The tunnel oxide layer has a thickness from about 70 .ANG. to about 120 .ANG..
    Type: Grant
    Filed: June 19, 1998
    Date of Patent: July 11, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ching-Hsiang Hsu, Mong-Song Liang, Steve S. Chung
  • Patent number: 5818085
    Abstract: A MOSFET device structure, on a silicon on insulator layer, in which a body contact to the silicon on insulator layer exists, has been developed. The MOSFET device structure features a heavily doped P type body contact region in a lightly doped source and drain region of the MOSFET device structure, formed from an ion implantation through a metal silicide layer. The addition of the body contact results in more controllable device characteristics, in terms of drain currents, etc., than for counterparts fabricated in silicon on insulator layer, without the use of a body contact.
    Type: Grant
    Filed: July 14, 1997
    Date of Patent: October 6, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hsiang Hsu, Shyh-Chyi Wong, Mong-Song Liang, Steve S. Chung
  • Patent number: 5728613
    Abstract: A process has been developed in which narrow base width, lateral bipolar junction transistors, and narrow channel length MOSFET devices, can be simultaneously fabricated, in a silicon on insulator layer. The narrow base width is defined by the width of an insulator sidewall spacer, formed on the sides of a polysilicon gate structure. The narrow base width, resulting in increased transistor gain and switching speed, along with reductions in parasitic capacitances, due to placing devices in a silicon on insulator layer, result in enhanced device performance.
    Type: Grant
    Filed: March 27, 1996
    Date of Patent: March 17, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hsiang Hsu, Steve S. Chung, Shyh-Chyi Wong, Mong-Song Liang
  • Patent number: 5705839
    Abstract: A process has been developed in which narrow base width, lateral bipolar junction transistors, and narrow channel length MOSFET devices, can be simultaneously fabricated, using a silicon on insulator approach. Insulator sidewall spacer and gate processing is used to produce narrow base widths for enhanced collector-base device characteristics, in terms of transistor gain, switching speeds and junction breakdowns.
    Type: Grant
    Filed: May 16, 1997
    Date of Patent: January 6, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hsiang Hsu, Shyh-Chyi Wong, Mong-Song Liang, Steve S. Chung
  • Patent number: 5610087
    Abstract: A process has been developed in which narrow base width, lateral bipolar junction transistors, and short channel length MOSFET devices, can be simultaneously fabricated, in a silicon on insulator layer. The narrow base width is defined by the width of an insulator sidewall spacer, formed on the sides of a polysilicon gate structure. The narrow base width, resulting in increased transistor gain and switching speed, along with reductions in parasitic capacitances, due to placing devices in a silicon on insulator layer, result in enhanced device performance.
    Type: Grant
    Filed: November 9, 1995
    Date of Patent: March 11, 1997
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ching-Hsiang Hsu, Shyh-Chyi Wong, Mong-Song Liang, Steve S. Chung
  • Patent number: 5573961
    Abstract: A process for fabricating a MOSFET device, on a silicon on insulator layer, in which a body contact to the silicon on insulator layer exists, has been developed. The process features creating a heavily doped P type body contact region in a lightly doped source and drain region of the MOSFET, via ion implantation through a metal silicide layer. The addition of the body contact results in more controllable device characteristics, in terms of drain currents, etc., than for counterparts fabricated in silicon on insulator layer, without the use of a body contact.
    Type: Grant
    Filed: November 9, 1995
    Date of Patent: November 12, 1996
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ching-Hsiang Hsu, Shyh-Chyi Wong, Mong-Song Liang, Steve S. Chung
  • Patent number: 5567631
    Abstract: A process has been developed in which narrow base width, lateral bipolar junction transistors, and narrow channel length MOSFET devices, can be simultaneously fabricated, using a silicon on insulator approach. Insulator sidewall spacer and gate processing is used to produce narrow base widths for enhanced collector--base device characteristics, in terms of transistor gain, switching speeds and junction breakdowns.
    Type: Grant
    Filed: November 13, 1995
    Date of Patent: October 22, 1996
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ching-Hsiang Hsu, Shyh-Chyi Wong, Mong-Song Liang, Steve S. Chung