Patents by Inventor Steve S. S. Chiang

Steve S. S. Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5510730
    Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open reconfigurable programmable elements situated at the intersection of any two segments to be connected.
    Type: Grant
    Filed: June 21, 1995
    Date of Patent: April 23, 1996
    Assignee: Actel Corporation
    Inventors: Abbas El Gamal, Steve S. S. Chiang
  • Patent number: 5367208
    Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.
    Type: Grant
    Filed: January 13, 1993
    Date of Patent: November 22, 1994
    Assignee: Actel Corporation
    Inventors: Abbas El Gamal, Steve S. S. Chiang
  • Patent number: 5187393
    Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable elements situated at the intersection of any two segments to be connected.
    Type: Grant
    Filed: April 15, 1992
    Date of Patent: February 16, 1993
    Assignee: Actel Corporation
    Inventors: Abbas El Gamal, Steve S. S. Chiang
  • Patent number: 5015885
    Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn by programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open reconfigurable programmable elements situated at the intersection of any two segments to be connected. Sensing circuitry and wiring may be included to allow 100% observability of internal circuit nodes, such as module outputs, from an external pad interface.
    Type: Grant
    Filed: February 10, 1989
    Date of Patent: May 14, 1991
    Assignee: Actel Corporation
    Inventors: Abbas El Gamal, Steve S. S. Chiang