Abstract: Advantage is taken of Very Large Scale Integrated (VLSI) circuit design and manufacture to provide, in a digital data handling system handling display signal streams, a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor has, on a single VLSI device, a plurality of processors which cooperate for generating video signal streams and which employ distinctive addressing modes for memory elements of the device. Each of the plurality of processors has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors, and further has registers for controlling access, and the modes of access, to data held in memory.

Abstract: A digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors. Most audio and/or video compression algorithms use a Huffman style bit compression scheme with compression codes in variable length bit fields. The compressed data is a compacted bit stream which must be interpreted serially in order to extract the codes. In contrast to most microprocessors which process bit streams only inefficiently, the present invention uses a serialization FIFO to provide a hardware assist to the Huffman encoding/decoding.

Abstract: Advantage is taken of Very Large Scale Integrated (VLSI) circuit design and manufacture to provide, in a digital data handling system handling display signal streams, a video processor which is capable of high performance due to vector processing and special addressing modes. A single VLSI device has a plurality of processors which cooperate for generating video signal streams and which employ distinctive addressing modes for memory elements of the device. Each of the plurality of processors has associated instruction and data caches, and the processors are joined together by a wide data bus formed on the same substrate as the processors. Each processor has a load/store unit, a translation unit associated with the load/store unit, and an index control register for controlling any translation of data bit streams passed through the load/store unit.

Abstract: A digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors.

Abstract: A digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors. Any graphics subsystem must be able to support a variety of video formats, causing video refresh logic to become complicated. Such potential complications are avoided by the provision of a simple, general purpose hardware refresh system based on the direct color graphics frame buffer, with the broader range of services being provided by emulation using one of the processors included in the device.

Abstract: Advantage is taken of Very Large Scale Integrated (VLSI) circuit design and manufacture to provide, in a digital data handling system handling display signal streams, a video processor which is capable of high performance due to vector processing and asynchronous interrupt service. The VLSI device has a plurality of processors which cooperate for generating video signal streams and at least one and preferably at least two interrupt registers for controlling the operations of instruction data stream execution and interruption.