Patents by Inventor Steve Tsai

Steve Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Shared cache structure for temporal and non-temporal instructions
    Patent number: 6584547
    Abstract: A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: June 24, 2003
    Assignee: Intel Corporation
    Inventors: Salvador Palanca, Niranjan L. Cooray, Angad Narang, Vladimir Pentkovski, Steve Tsai
  • Shared cache structure for temporal and non-temporal instructions
    Publication number: 20020007441
    Abstract: A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.
    Type: Application
    Filed: March 9, 2001
    Publication date: January 17, 2002
    Inventors: Salvador Palanca, Niranjan L. Cooray, Angad Narang, Vladimir Pentkovski, Steve Tsai
  • Method and apparatus for implementing non-temporal loads
    Patent number: 6223258
    Abstract: A processor is described. The processor includes a decoder to decode instructions and a circuit, in response to a decoded instruction, to detect an incoming load instruction that misses a cache, allocate a buffer to service the incoming load instruction, and issue a bus request to load the data in the buffer without accessing said cache.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: April 24, 2001
    Assignee: Intel Corporation
    Inventors: Salvador Palanca, Vladimir Pentkovski, Steve Tsai
  • Method and apparatus for implementing non-temporal stores
    Patent number: 6205520
    Abstract: A processor is disclosed. The processor includes a decoder to decode instructions and a circuit, in response to a decoded instruction, detects an incoming write back or write through streaming store instruction that misses a cache and allocates a buffer in write combining mode. The circuit, in response to a second decoded instruction, detects either an uncacheable speculative write combining store instruction or a second write back streaming store or write through streaming store instruction that hits the buffer and merges the second decoded instruction with the buffer.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: March 20, 2001
    Assignee: Intel Corporation
    Inventors: Salvador Palanca, Vladimir Pentkovski, Steve Tsai, Subramaniam Maiyuran
  • Shared cache structure for temporal and non-temporal information using indicative bits
    Patent number: 6202129
    Abstract: A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: March 13, 2001
    Assignee: Intel Corporation
    Inventors: Salvador Palanca, Niranjan L. Cooray, Angad Narang, Vladimir Pentkovski, Steve Tsai