Abstract: A method of DNA base-calling from a nanochannel DNA sequencer. The method includes building a reference map and preparing an unknown sequence of DNA prior to the final step of data matching. The reference map includes a series of reference characters, such as numbers, that describe the change in tunneling current of a DNA strand with a known sequence. A DNA strand of unknown sequence is prepared so that the change in electrical measurement can also be described numerically. The section of match between the DNA strand of unknown sequence and the reference map is used to determine the sequence of the DNA strand.

Abstract: A method of fabricating a sensing device for DNA sequencing and biomolecule characterization including the steps of fabricating a microelectrode chip having a silicon substrate and a silicon nitride diaphragm, attaching a monolayer graphene sheet to the silicon nitride diaphragm, dicing a portion of the monolayer graphene sheet to form a graphene microribbon, converting the graphene microribbon to a graphene nanoribbon, and converting the graphene nanoribbon to a carbyne. A sensing device for DNA sequencing and biomolecule characterization is also disclosed. The sensing device includes a silicon substrate, a cavity in the silicon substrate covered by a silicon nitride layer, microelectrodes attached to the silicon nitride layer, graphene covering the microelectrodes, and carbyne attached to a portion of the silicon nitride layer covering said cavity.

Abstract: A process for fabricating a nanochannel system using a combination of microelectromechanical system (MEMS) microfabrication techniques, atomic force microscopy (AFM) nanolithography, and focused ion beam (FIB). The nanochannel system, fabricated on either a glass or silicon substrate, has channel heights and widths on the order of single to tens of nanometers. The channel length is in the micrometer range. The nanochannel system is equipped with embedded micro and nanoscale electrodes, positioned along the length of the nanochannel for electron tunneling based characterization of nanoscale particles in the channel. Anodic bonding is used to cap off the nanochannel with a cover chip.

Abstract: A process for fabricating a nanochannel system using a combination of microelectromechanical system (MEMS) microfabrication techniques, atomic force microscopy (AFM) nanolithography, and focused ion beam (FIB). The nanochannel system, fabricated on either a glass or silicon substrate, has channel heights and widths on the order of single to tens of nanometers. The channel length is in the micrometer range. The nanochannel system is equipped with embedded micro and nanoscale electrodes, positioned along the length of the nanochannel for electron tunneling based characterization of nanoscale particles in the channel. Anodic bonding is used to cap off the nanochannel with a cover chip.

Abstract: A process for fabricating a nanochannel system using a combination of microelectromechanical system (MEMS) microfabrication techniques, atomic force microscopy (AFM) nanolithography, and focused ion beam (FIB). The nanochannel system, fabricated on either a glass or silicon substrate, has channel heights and widths on the order of single to tens of nanometers. The channel length is in the micrometer range. The nanochannel system is equipped with embedded micro and nanoscale electrodes, positioned along the length of the nanochannel for electron tunneling based characterization of nanoscale particles in the channel. Anodic bonding is used to cap off the nanochannel with a cover chip.

Abstract: A process for fabricating a nanochannel system using a combination of microelectromechanical system (MEMS) microfabrication techniques and atomic force microscopy (AFM) nanolithography. The nanochannel system, fabricated on either a glass or silicon substrate, has channel heights and widths on the order of single to tens of nanometers. The channel length is in the micrometer range. The nanochannel system is equipped with embedded micro or nanoscale electrodes, positioned along the length of the nanochannel for electron tunneling based characterization of nanoscale particles in the channel. Anodic bonding is used to cap off the nanochannel with a cover chip.

Abstract: An impedance biosensor for detecting a contaminant in a starting material, the biosensor comprising a housing, an input device supported by the housing, an output device supported by the housing, a microfluidic cell supported by the housing, the starting material being engagable with the microfluidic cell, and an impedance analyzer supported by the housing and operable to measure impedance of the starting material to detect the presence of a contaminant.

Abstract: A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated.

Abstract: A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated.

Abstract: A cache memory having a mechanism for managing offset and aliasing conditions is disclosed. In accordance with a preferred embodiment of the invention, the cache memory comprises a first directory circuit, a second directory circuit, a multiple number of most recently used bits, and a multiple number of set/reset circuits. The first directory circuit, having multiple caches lines, is utilized to receive partial effective addresses. The second directory circuit is utilized to receive an output from the first directory circuit. A most recently used bit is associated with each cache line within the first directory circuit. The set/reset circuit, coupled to each of the most recently used bits, is utilized to set one of the most recently used bits to a first state while concurrently resetting the rest of the most recently used bits to a second state within a single cycle during an occurrence of an offset or aliasing conditions such that offset or aliasing conditions can be more efficiently managed.