Abstract: A Random Access Memory (RAM) with improved memory access time supporting simultaneous transitions of an address signal and a write enable signal while preventing accidental writes. The RAM includes a memory array, an address transition detector and a race detector. Operation of the memory array is controlled by the address signal and a write clock signal. In response to the write clock's read state the memory array reads data from an address represented by the address signal, while the write clock's write state causes the memory array to write data at the address represented by the address signal. The address transition detector and race detector work together to generate the write clock signal. The address transition detector generates an address transition signal when it detects a transition of the address signal from a representation of a first address of the memory array to a representation of a second address of the memory array.

Abstract: The present invention is dynamic pulse generator for generating an output pulse from a first input pulse and a second input pulse, where the output pulse is guaranteed to have a pulse width of at least the pulse width of whichever of the two input pulses has a delayed leading edge with respect to the other. The first input pulse has a first leading edge and a first trailing edge. The second input pulse has a second leading edge and a second trailing edge. The second leading edge is delayed from the first leading edge. An edge detector detects the second leading edge, and outputs a first predetermined level when the second leading edge is detected. The edge detector also detects the first trailing edge and the second trailing edge and outputs a second predetermined level. A latch is responsive to the edge detector and generates a signal indicating that the second leading edge has been detected.