Abstract: A junction field effect transistor and a bipolar transistor are merged in a single composite device disposed within a single isolation region by the use of planar processing techniques. The device includes an annular source region formed within a semiconductor body portion constituting a collector zone. Within the central portion of the collector zone circumscribed by the annular source region there is formed an emitter zone nested within a region that constitutes both the drain region of the JFET and the base zone of the bipolar transistor. An annular channel region connects the annular source region and the central drain region. An annular region forming a semiconductor junction with the annular channel adjacent to the annular source region constitutes one of two gate regions of the JFET. The other gate region is constituted by the body portion serving as the collector zone.