Patents by Inventor Steve W. Otto

Steve W. Otto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for performing distributed simulation utilizing a simulation backplane
    Patent number: 7319947
    Abstract: A method and apparatus for performing distributed simulation is presented. According to an embodiment of the present invention, simulators are interfaced to a simulation backplane via simulator-dependent interfaces (SDI's). The simulators exchange messages via the simulation backplane and the SDI's. The SDI's convert the exchanged messages between a data format supported by the backplane and a data format supported by the simulator to which the interface is connected. By interfacing the simulators with the backplane via SDI's, the validation environment may be changed without reconfiguring the backplane.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: January 15, 2008
    Assignee: Intel Corporation
    Inventors: Manpreet S. Khaira, Erik M. Seligman, Jeremy S. Casas, Steve W. Otto, Mandar S. Joshi
  • Logic verification in large systems
    Patent number: 7171347
    Abstract: A method of preparing a circuit model for simulation comprises decomposing the circuit model having a number of latches into a plurality of extended latch boundary components and partitioning the plurality of extended latch boundary components. Decomposing and partitioning the circuit model may include decomposing hierarchical cells of the circuit model, and using a constructive bin-packing heuristic to partition the plurality of extended latch boundary components. The partitioned circuit model is compiled, and simulated on a uni-processor, a multi-processor, or a distributed processing computer system.
    Type: Grant
    Filed: July 2, 1999
    Date of Patent: January 30, 2007
    Assignee: Intel Corporation
    Inventors: Manpreet S. Khaira, Steve W. Otto, Honghua H. Yang, Mandar S. Joshi, Jeremy S. Casas, Erik M. Seligman
  • LOGIC VERIFICATION IN LARGE SYSTEMS
    Publication number: 20030163297
    Abstract: A method of preparing a circuit model for simulation comprises decomposing the circuit model having a number of latches into a plurality of extended latch boundary components and partitioning the plurality of extended latch boundary components. Decomposing and partitioning the circuit model may include decomposing hierarchical cells of the circuit model, and using a constructive bin-packing heuristic to partition the plurality of extended latch boundary components. The partitioned circuit model is compiled, and simulated on a uni-processor, a multi-processor, or a distributed processing computer system.
    Type: Application
    Filed: July 2, 1999
    Publication date: August 28, 2003
    Inventors: MANPREET S. KHAIRA, STEVE W. OTTO, HONGHUA H. YANG, MANDAR S. JOSHI, JEREMY S. CASAS, ERIK M. SELIGMAN