Abstract: Methods, systems, and storage media for running unified simulations on clusters. Exemplary implementations may include: receiving simulation parameters for a simulation of a cluster; generating synthesized workload events based the simulation parameters of the cluster; determining a memory latency associated with the cluster; determining a reliability and availability of resources in the cluster for a predetermined duration of time; simulating events for jobs in the cluster based on the reliability and availability of resources in the cluster, each job associated with one or more synthesized workload events; and outputting simulation results based on the synthesized workload, the memory latency, and the events.

Abstract: The present disclosure relates to recombinant transcriptional repressor polypeptides that are capable of being targeted to specific loci, as well as methods of using these recombinant polypeptides for reducing expression of a target nucleic acid in plants.

Abstract: Techniques disclosed herein relate to operating a motor using a first control module and a second control module. The techniques may involve detecting, by the first control module, after loading application code for execution by the first control module and the second control module, an anomalous condition. The techniques may further involve in response to detection of the anomalous condition, disabling, by the first control module, input power to the motor. The techniques may further involve resetting the first control module and the second control module to a boot loader stage.

Abstract: A series of peptide-drug conjugates that react with multi-arm polyethylene glycol (PEG) to form chemically cross-linked hydrogels and their use as both a sealant and a therapeutic depot is disclosed.

Abstract: An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.

Abstract: A post and cap assembly for chain link fence is provided, including a tubular post with an upper end, an outer surface and an inner surface. A cap is dimensioned for telescoping engagement with the upper end, the cap having an exterior surface, an interior surface and a depending skirt. At least one depending formation extends from the interior surface for engaging the post upper end, as the skirt engages the outer surface.

Abstract: An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.

Abstract: A post and cap assembly for chain link fence is provided, including a tubular post with an upper end, an outer surface and an inner surface. A cap is dimensioned for telescoping engagement with the upper end, the cap having an exterior surface, an interior surface and a depending skirt. At least one depending formation extends from the interior surface for engaging the post upper end, as the skirt engages the outer surface.

Abstract: A post and cap assembly for chain link fence is provided, including a tubular post with an upper end, an outer surface and an inner surface. A cap is dimensioned for telescoping engagement with the upper end, the cap having an exterior surface, an interior surface and a depending skirt. At least one depending formation extends from the interior surface for engaging the post upper end, as the skirt engages the outer surface.

Abstract: An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.

Abstract: An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.

Abstract: Methods, apparatuses, and system for performing at least one of error correction or error detection are described. In one embodiment, a radio frequency identification (RFID) tag receives a signal activating or interrogating the tag. The tag includes memory that stores data associated with the tag. The tag performs at least one of error detection or error correction on the stored data. The error detection includes detecting, by the tag, that one or more bits of the stored data are inflicted with an error. The error correction includes correcting the erroneous bit if the error affects less than a predetermined number of the bits of the stored data. The tag transmits the stored data to a reader in response to the detection or correction. The reader can analyze the stored data for additional information about the error or provide the stored data to another computing system that performs the analysis.

Abstract: Systems and devices for improving the efficiency of secondary electron detection in charged particle beam systems include a charged particle detector, a first elongate member coupled with the charged particle detector, and a second elongate member coupled with the charged particle detector. The first elongate member and the second elongate member each extend away from the charged particle detector. The system also includes at least one drawing member that is coupled with the first elongate member. Additionally, at least one electrical connection point is arranged to supply at least one bias voltage to the first elongate member, the second elongate member, and the drawing member. The drawing member is configured to generate an electromagnetic field that applies a drawing force that draws charged particles away from the charged particle source, and/or reduces the amount of charged particles from the charged particle source that strike the charged particle tool.

Abstract: Systems and devices for improving the efficiency of secondary electron detection in charged particle beam systems include a charged particle detector, a first elongate member coupled with the charged particle detector, and a second elongate member coupled with the charged particle detector. The first elongate member and the second elongate member each extend away from the charged particle detector. The system also includes at least one drawing member that is coupled with the first elongate member. Additionally, at least one electrical connection point is arranged to supply at least one bias voltage to the first elongate member, the second elongate member, and the drawing member. The drawing member is configured to generate an electromagnetic field that applies a drawing force that draws charged particles away from the charged particle source, and/or reduces the amount of charged particles from the charged particle source that strike the charged particle tool.

Abstract: One aspect of the invention provides a system for radiation treatment of a tumor allowing for imaging of the tumor and a surrounding region during radiation therapy and to methods of using such a system. In one embodiment, the system includes a number of radiation detectors positioned in an array to detect radiation scattered from the tumor and the surrounding region. A 3-dimensional image of the tumor is reconstructed from the 2-dimensional scattered radiation projections.

Abstract: An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.

Abstract: A post and cap assembly for chain link fence is provided, including a tubular post with an upper end, an outer surface and an inner surface. A cap is dimensioned for telescoping engagement with the upper end, the cap having an exterior surface, an interior surface and a depending skirt. At least one depending formation extends from the interior surface for engaging the post upper end, as the skirt engages the outer surface.

Abstract: A Power-on Reset circuit is described. The Power-on Reset is formed by two comparators and a latch circuit. The Power-on Reset circuit will de-assert the reset state once the supply voltage reaches a first reference point and re-assert the reset state once the supply voltage drops below a second reference point. The Power-on Reset circuit disclosed further includes circuits to initialize properly and to ensure the regulator voltage and the bandgap voltages are stable and above the ground level voltage.

Abstract: A Power-on Reset circuit is described. The Power-on Reset is formed by two comparators and a latch circuit. The Power-on Reset circuit will de-assert the reset state once the supply voltage reaches a first reference point and re-assert the reset state once the supply voltage drops below a second reference point. The Power-on Reset circuit disclosed further includes circuits to initialize properly and to ensure the regulator voltage and the bandgap voltages are stable and above the ground level voltage.

Abstract: One aspect of the invention provides a system for radiation treatment of a tumor allowing for imaging of the tumor and a surrounding region during radiation therapy and to methods of using such a system. In one embodiment, the system includes a number of radiation detectors positioned in an array to detect radiation scattered from the tumor and the surrounding region. A 3-dimensional image of the tumor is reconstructed from the 2-dimensional scattered radiation projections.