Abstract: A post and cap assembly for chain link fence is provided, including a tubular post with an upper end, an outer surface and an inner surface. A cap is dimensioned for telescoping engagement with the upper end, the cap having an exterior surface, an interior surface and a depending skirt. At least one depending formation extends from the interior surface for engaging the post upper end, as the skirt engages the outer surface.

Abstract: A post and cap assembly for chain link fence is provided, including a tubular post with an upper end, an outer surface and an inner surface. A cap is dimensioned for telescoping engagement with the upper end, the cap having an exterior surface, an interior surface and a depending skirt. At least one depending formation extends from the interior surface for engaging the post upper end, as the skirt engages the outer surface.

Abstract: A post and cap assembly for chain link fence is provided, including a tubular post with an upper end, an outer surface and an inner surface. A cap is dimensioned for telescoping engagement with the upper end, the cap having an exterior surface, an interior surface and a depending skirt. At least one depending formation extends from the interior surface for engaging the post upper end, as the skirt engages the outer surface.

Abstract: Methods, apparatuses, and system for performing at least one of error correction or error detection are described. In one embodiment, a radio frequency identification (RFID) tag receives a signal activating or interrogating the tag. The tag includes memory that stores data associated with the tag. The tag performs at least one of error detection or error correction on the stored data. The error detection includes detecting, by the tag, that one or more bits of the stored data are inflicted with an error. The error correction includes correcting the erroneous bit if the error affects less than a predetermined number of the bits of the stored data. The tag transmits the stored data to a reader in response to the detection or correction. The reader can analyze the stored data for additional information about the error or provide the stored data to another computing system that performs the analysis.

Abstract: One aspect of the invention provides a system for radiation treatment of a tumor allowing for imaging of the tumor and a surrounding region during radiation therapy and to methods of using such a system. In one embodiment, the system includes a number of radiation detectors positioned in an array to detect radiation scattered from the tumor and the surrounding region. A 3-dimensional image of the tumor is reconstructed from the 2-dimensional scattered radiation projections.

Abstract: A post and cap assembly for chain link fence is provided, including a tubular post with an upper end, an outer surface and an inner surface. A cap is dimensioned for telescoping engagement with the upper end, the cap having an exterior surface, an interior surface and a depending skirt. At least one depending formation extends from the interior surface for engaging the post upper end, as the skirt engages the outer surface.

Abstract: A Power-on Reset circuit is described. The Power-on Reset is formed by two comparators and a latch circuit. The Power-on Reset circuit will de-assert the reset state once the supply voltage reaches a first reference point and re-assert the reset state once the supply voltage drops below a second reference point. The Power-on Reset circuit disclosed further includes circuits to initialize properly and to ensure the regulator voltage and the bandgap voltages are stable and above the ground level voltage.

Abstract: A Power-on Reset circuit is described. The Power-on Reset is formed by two comparators and a latch circuit. The Power-on Reset circuit will de-assert the reset state once the supply voltage reaches a first reference point and re-assert the reset state once the supply voltage drops below a second reference point. The Power-on Reset circuit disclosed further includes circuits to initialize properly and to ensure the regulator voltage and the bandgap voltages are stable and above the ground level voltage.

Abstract: One aspect of the invention provides a system for radiation treatment of a tumor allowing for imaging of the tumor and a surrounding region during radiation therapy and to methods of using such a system. In one embodiment, the system includes a number of radiation detectors positioned in an array to detect radiation scattered from the tumor and the surrounding region. A 3-dimensional image of the tumor is reconstructed from the 2-dimensional scattered radiation projections.

Abstract: A Power-on Reset circuit is described. The Power-on Reset is formed by two comparators and a latch circuit. The Power-on Reset circuit will de-assert the reset state once the supply voltage reaches a first reference point and re-assert the reset state once the supply voltage drops below a second reference point. The Power-on Reset circuit disclosed further includes circuits to initialize properly and to ensure the regulator voltage and the bandgap voltages are stable and above the ground level voltage.

Abstract: Disclosed is a fractional bandgap circuit and method to provide a same reference voltage value in a variety of circumstances of operation, including variations in manufacturing process, temperature, and a supply voltage. The disclosed fractional bandgap circuit and method also allows for low supply voltage operation within a compact layout area.

Abstract: An input power on a tag is monitored. An input impedance of the tag is adjusted based on the monitored input power to increase a backscatter level of the tag. In one embodiment, an output voltage of a rectifier device is monitored. An input power to the tag is determined based on the output voltage. An input impedance of the tag is adjusted based on the input power to increase the backscatter level of the tag.

Abstract: A method of programming one-time programmable (OTP) memory cells in an array is described. Each memory cell has a MOSFET programming element and a MOSFET pass transistor, the MOSFET pass transistor having a gate electrode over a channel region between two source/drain regions, and the MOSFET programming element having a gate electrode over a channel region contiguous to a source/drain region either part of, or connected to, one of the two source/drains associated with the MOSFET pass transistor. The other source/drain region of the MOSFET pass transistor is coupled to a bit line. The memory cell is programmed by setting a first voltage of a first polarity on the gate electrode of the pass transistor to electrically connect the source/drain regions of the pass transistor; setting a second voltage of the first polarity on the gate electrode of the programming element; and setting a third voltage of a second polarity on the bit line.

Abstract: A circuit arrangement and method of reading the logic state of a memory cell in an array of semiconductor memory cells. A data memory cell selected from the array drives a current on a first data bit line in a read operation. A reference memory cell corresponding to the memory cell is activated after the memory cell is selected, the reference memory cell driving a current through the reference data line at a greater rate than that of the corresponding memory cell regardless of the logic state of the memory cell. A sense amplifier connected to the data line and a reference data line determines the logic state of the selected memory cell. A delay circuit activates the reference memory cell after the memory cell is selected and enables the sense amplifier after the reference memory cell has been activated.

Abstract: Methods, apparatuses, and system for performing at least one of error correction or error detection are described. In one embodiment, a radio frequency identification (RFID) tag receives a signal activating or interrogating the tag. The tag includes memory that stores data associated with the tag. The tag performs at least one of error detection or error correction on the stored data. The error detection includes detecting, by the tag, that one or more bits of the stored data are inflicted with an error. The error correction includes correcting the erroneous bit if the error affects less than a predetermined number of the bits of the stored data. The tag transmits the stored data to a reader in response to the detection or correction. The reader can analyze the stored data for additional information about the error or provide the stored data to another computing system that performs the analysis.

Abstract: Disclosed is a fractional bandgap circuit and method to provide a same reference voltage value in a variety of circumstances of operation, including variations in manufacturing process, temperature, and a supply voltage. The disclosed fractional bandgap circuit and method also allows for low supply voltage operation within a compact layout area.

Abstract: An input power on a tag is monitored. An input impedance of the tag is adjusted based on the monitored input power to increase a backscatter level of the tag. In one embodiment, an output voltage of a rectifier device is monitored. An input power to the tag is determined based on the output voltage. An input impedance of the tag is adjusted based on the input power to increase the backscatter level of the tag.

Abstract: A circuit arrangement and method of reading the logic state of a memory cell in an array of semiconductor memory cells. A data memory cell selected from the array drives a current on a first data bit line in a read operation. A reference memory cell corresponding to the memory cell is activated after the memory cell is selected, the reference memory cell driving a current through the reference data line at a greater rate than that of the corresponding memory cell regardless of the logic state of the memory cell. A sense amplifier connected to the data line and a reference data line determines the logic state of the selected memory cell. A delay circuit activates the reference memory cell after the memory cell is selected and enables the sense amplifier after the reference memory cell has been activated.

Abstract: A method of programming one-time programmable (OTP) memory cells in an array is described. Each memory cell has a MOSFET programming element and a MOSFET pass transistor, the MOSFET pass transistor having a gate electrode over a channel region between two source/drain regions, and the MOSFET programming element having a gate electrode over a channel region contiguous to a source/drain region either part of, or connected to, one of the two source/drains associated with the MOSFET pass transistor. The other source/drain region of the MOSFET pass transistor is coupled to a bit line. The memory cell is programmed by setting a first voltage of a first polarity on the gate electrode of the pass transistor to electrically connect the source/drain regions of the pass transistor; setting a second voltage of the first polarity on the gate electrode of the programming element; and setting a third voltage of a second polarity on the bit line.

Abstract: A Power-on Reset circuit is described. The Power-on Reset is formed by two comparators and a latch circuit. The Power-on Reset circuit will de-assert the reset state once the supply voltage reaches a first reference point and re-assert the reset state once the supply voltage drops below a second reference point. The Power-on Reset circuit disclosed further includes circuits to initialize properly and to ensure the regulator voltage and the bandgap voltages are stable and above the ground level voltage.