Patents by Inventor Steve Woolet

Steve Woolet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Prefetching with multiple processors and threads via a coherency bus
    Patent number: 8543767
    Abstract: A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: September 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Gordon B. Bell, Gordon T. Davis, Jeffrey H. Derby, Anil Krishna, Srinivasan Ramani, Ken Vu, Steve Woolet
  • EFFECTIVE PREFETCHING WITH MULTIPLE PROCESSORS AND THREADS
    Publication number: 20120246406
    Abstract: A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.
    Type: Application
    Filed: June 4, 2012
    Publication date: September 27, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gordon Bernard Bell, Gordon Taylor Davis, Jeffrey Haskell Derby, Anil Krishna, Srinivasan Ramani, Ken Vu, Steve Woolet
  • Effective prefetching with multiple processors and threads
    Patent number: 8200905
    Abstract: A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: June 12, 2012
    Assignee: International Business Machines Corporation
    Inventors: Gordon Bernard Bell, Gordon Taylor Davis, Jeffrey Haskell Derby, Anil Krishna, Srinivasan Ramani, Ken Vu, Steve Woolet
  • SNOOP-BASED PREFETCHING
    Publication number: 20100042786
    Abstract: A processing system is disclosed. The processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.
    Type: Application
    Filed: August 14, 2008
    Publication date: February 18, 2010
    Applicant: International Business Machines Corporation
    Inventors: Gordon Bernard BELL, Gordon Taylor DAVIS, Jeffrey Haskell DERBY, Anil KRISHNA, Srinivasan RAMANI, Ken VU, Steve WOOLET