Abstract: A switching rectifier circuit includes a pulse width modulation controller, a voltage switching circuit, a pulse width modulation comparator, an error amplifier, a voltage reference, a high threshold voltage comparator and a low threshold voltage comparator. A varying output voltage of the voltage regulator is sampled and compared to a high threshold voltage reference and a low threshold voltage reference. When the sampled output voltage is equal to or greater than the high threshold voltage reference the output voltage is decreased. When the sampled output voltage is equal to or less than the low threshold voltage reference the output voltage is increased.

Abstract: A system and method of providing an analog make before break circuit includes a first transistor coupled in series with a second transistor, the first transistor being configured for conducting a high portion of an input signal, the second transistor being configured for conducting a low portion of the input signal. A third transistor is configured to interrupt a connection between the input signal and a first transistor input node, the third transistor having a third transistor threshold voltage between of about 90 and about 110 percent of a second transistor threshold voltage. A fourth transistor is configured to interrupt a connection between the input signal and a second transistor input node, the fourth transistor having a fourth transistor threshold voltage of between about 90 and about 110 percent of a first transistor threshold voltage.

Abstract: A switching rectifier circuit includes a pulse width modulation controller, a voltage switching circuit, a pulse width modulation comparator, an error amplifier, a voltage reference, a high threshold voltage comparator and a low threshold voltage comparator. A varying output voltage of the voltage regulator is sampled and compared to a high threshold voltage reference and a low threshold voltage reference. When the sampled output voltage is equal to or greater than the high threshold voltage reference the output voltage is decreased. When the sampled output voltage is equal to or less than the low threshold voltage reference the output voltage is increased.

Abstract: A soft-start generation system is configured to generate a soft-start voltage. The soft-start generation system includes sawtooth circuitry configured to generate current having a sawtooth waveform and staircase circuitry configured to generate current having an ascending staircase waveform. A ramp-up current may be generated that is a combination of the sawtooth current and the staircase current. The ramp-up current may continuously ramp up to a predetermined current level. The soft-start voltage may be generated based on the ramp-up current.

Abstract: A system and method of providing an analog make before break circuit includes a first transistor coupled in series with a second transistor, the first transistor being configured for conducting a high portion of an input signal, the second transistor being configured for conducting a low portion of the input signal. A third transistor is configured to interrupt a connection between the input signal and a first transistor input node, the third transistor having a third transistor threshold voltage between of about 90 and about 110 percent of a second transistor threshold voltage. A fourth transistor is configured to interrupt a connection between the input signal and a second transistor input node, the fourth transistor having a fourth transistor threshold voltage of between about 90 and about 110 percent of a first transistor threshold voltage.

Abstract: An electronic circuit may output a slope compensation signal for performance of slope compensation of a current mode switching regulator. The circuit may generate a voltage across a storage device that is supplied to a voltage-to-current converter, which may generate a first current in response to the supplied voltage. Current mirror circuitry may mirror the current and supply the mirrored current to the storage device to generate the voltage. The current mirror circuitry may also mirror the current to generate a second mirrored current, which may be supplied to an output of the electronic circuit. In addition to using the first mirrored current to generate the voltage, the voltage may be generated by pulling down the voltage to ground in accordance with a duty cycle of a switching signal used for generation of an output of the current mode switching regulator.

Abstract: A soft-start generation system is configured to generate a soft-start voltage. The soft-start generation system includes sawtooth circuitry configured to generate current having a sawtooth waveform and staircase circuitry configured to generate current having an ascending staircase waveform. A ramp-up current may be generated that is a combination of the sawtooth current and the staircase current. The ramp-up current may continuously ramp up to a predetermined current level. The soft-start voltage may be generated based on the ramp-up current.

Abstract: Techniques and circuits are described by which analog circuits may be quickly driven to desired states at startup in a fast and accurate manner.

Abstract: Delay circuits are described for which the delay remains substantially constant within a desired range of variation of supply voltage and/or temperature.

Abstract: Delay circuits are described for which the delay remains substantially constant within a desired range of variation of supply voltage and/or temperature.

Abstract: Techniques and circuits are described by which analog circuits may be quickly driven to desired states at startup in a fast and accurate manner.

Abstract: An electronic product includes an application specific semiconductor chip (ASIC) device which includes in its circuitry both a linear regulator module configured to be coupled to an optional external capacitance and a capless regulator module configured to be coupled to internal capacitance of the electronic product. Control logic of the ASIC device is responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device. The control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation.

Abstract: A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

Abstract: Methods and systems for automatically and/or locally adjusting power-valid detection. In one class of embodiments, local power-on-reset circuits are included in individual power islands; in another class of embodiments, the power-on-reset circuit is automatically reprogrammed, depending on the detected interface voltage level, to use the same circuitry for power-valid detection in either case.

Abstract: Methods and systems for automatically and/or locally adjusting power-valid detection. In one class of embodiments, local power-on-reset circuits are included in individual power islands; in another class of embodiments, the power-on-reset circuit is automatically reprogrammed, depending on the detected interface voltage level, to use the same circuitry for power-valid detection in either case.

Abstract: An electronic product includes an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product. The capless regulator module includes both a low-power sub-module and a high-power sub-module. Control logic of the ASIC is configured to determine if an external capacitance is present. If so, the control logic causes the high-power capless regulator sub-module to be used during a power-up phase of the ASIC; if not, only the low-power capless regulator sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

Abstract: An electronic product includes an application specific semiconductor chip (ASIC) device which includes in its circuitry both a linear regulator module configured to be coupled to an optional external capacitance and a capless regulator module configured to be coupled to internal capacitance of the electronic product. Control logic of the ASIC device is responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device. The control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation.

Abstract: A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

Abstract: A method for operating an electronic product having an application specific semiconductor chip (ASIC) device which includes in its circuitry both a linear regulator module configured to be coupled to an optional external capacitance and a capless regulator module configured to be coupled to internal capacitance of the electronic product utilizes control logic of the ASIC device responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device. The control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation.