Abstract: An optical switch network (4) includes optical routers (10), which route information in optical fibers (12). Each fiber carries a plurality of data channels (20), collectively a data channel group (14), and a control channel (16). Data is carried on the data channels in data bursts and control information is carried on the control channel (18) in burst header packets. A burst header packet includes routing information for an associated data burst (28) and precedes its associated data burst. Parallel scheduling at multiple delays may be used for faster scheduling. In one embodiment, unscheduled times and gaps may be processed in a unified memory for more efficient operation.

Abstract: An algorithm is presented along with circuitry for implementing same to accomplish the interface of a pair of synchronized data lines with a pair of non-synchronized data lines using data buffers where there can be as few as three cells of data buffers to accomplish reading data out and writing data in without interfering one with the other. This algorithm is accomplished by measuring the time skew between overhead bits of the two non-syncrhonized data streams and writing to the frame most recently read by the synchronized data stream based on an algorithm formulated in view of or based on a function of the time skew.

Abstract: A frame synchronization circuit is illustrated, which uses an algorithm of reverting to an initial state of selecting the next logic zero data bit in a data bit stream for the potential bit position to be used as a framing bit, and returning to reinitialization if any of the next M-bits in that bit position do not follow a prescribed framing pattern. Once synchronization is established, the detection of three out of five framing bits being in error will cause the circuit to return to an intermediate state in the framing process, whereby any further errors in the next X number of bits will cause reinitialization, but the lack of any further errors in the next X-bits will allow the circuit to confirm that its original bit position choice as framing bit was correct. This allows the circuit to continue operation with the assurance that it is correctly synchronized with the data, and without interrupting data flow for the comparatively long time it takes to synchronize from "scratch".