Patents by Inventor Steven A. Atherton
Steven A. Atherton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11887924Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.Type: GrantFiled: November 23, 2022Date of Patent: January 30, 2024Assignee: Cirrus Logic Inc.Inventors: Craig McAdam, Jonathan Taylor, Douglas Macfarlane, John Kerr, James Munger, John Pavelka, Steven A. Atherton
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Publication number: 20230088252Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.Type: ApplicationFiled: November 23, 2022Publication date: March 23, 2023Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Craig MCADAM, Jonathan TAYLOR, Douglas MACFARLANE, John KERR, James MUNGER, John PAVELKA, Steven A. ATHERTON
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Patent number: 11562952Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.Type: GrantFiled: April 30, 2021Date of Patent: January 24, 2023Assignee: Cirrus Logic, Inc.Inventors: Craig McAdam, Jonathan Taylor, Douglas Macfarlane, John Kerr, James Munger, John Pavelka, Steven A. Atherton
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Publication number: 20220285299Abstract: A semiconductor die may be coupled to a printed circuit board using a solder ball. The semiconductor die comprises a redistribution layer formed above a semiconductor chip, a polymer layer formed on the redistribution layer, and an Under Bump Metallurgy (UBM) layer formed on the polymer layer. The polymer layer comprises a plurality of vias, which electrically couple the UBM layer to the redistribution layer. The entire UBM layer may be deposited with a continuously flat upper surface for coupling to the solder ball. The plurality of vias may be positioned such that they are centered on a point that is not central to the UBM layer.Type: ApplicationFiled: May 19, 2022Publication date: September 8, 2022Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Yaoyu PANG, Steven A. ATHERTON
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Publication number: 20220246514Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.Type: ApplicationFiled: April 30, 2021Publication date: August 4, 2022Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Craig MCADAM, Jonathan TAYLOR, Douglas MACFARLANE, John KERR, James MUNGER, John PAVELKA, Steven A. ATHERTON
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Patent number: 11373968Abstract: A semiconductor die may be coupled to a printed circuit board using a solder ball. The semiconductor die comprises a redistribution layer formed above a semiconductor chip, a polymer layer formed on the redistribution layer, and an Under Bump Metallurgy (UBM) layer formed on the polymer layer. The polymer layer comprises a plurality of vias, which electrically couple the UBM layer to the redistribution layer. The entire UBM layer may be deposited with a continuously flat upper surface for coupling to the solder ball. The plurality of vias may be positioned such that they are centered on a point that is not central to the UBM layer.Type: GrantFiled: April 24, 2020Date of Patent: June 28, 2022Assignee: Cirrus Logic, Inc.Inventors: Yaoyu Pang, Steven A. Atherton
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Publication number: 20200343206Abstract: A semiconductor die may be coupled to a printed circuit board using a solder ball. The semiconductor die comprises a redistribution layer formed above a semiconductor chip, a polymer layer formed on the redistribution layer, and an Under Bump Metallurgy (UBM) layer formed on the polymer layer. The polymer layer comprises a plurality of vias, which electrically couple the UBM layer to the redistribution layer. The entire UBM layer may be deposited with a continuously flat upper surface for coupling to the solder ball. The plurality of vias may be positioned such that they are centered on a point that is not central to the UBM layer.Type: ApplicationFiled: April 24, 2020Publication date: October 29, 2020Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Yaoyu PANG, Steven A. ATHERTON
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Patent number: 10049988Abstract: A method for forming a semiconductor device package substrate including a fiducial mark is provided. The method of forming the package substrate includes forming a dielectric layer over a lower portion of the package substrate. A metal layer is formed over a fiducial region of the package substrate. The metal layer is etched to form a first signal line in the fiducial region. A passivation layer is formed over the first signal line. The passivation layer is etched over the first signal line to form a fiducial mark.Type: GrantFiled: March 2, 2017Date of Patent: August 14, 2018Assignee: NXP USA, INC.Inventor: Steven A. Atherton
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Publication number: 20170179038Abstract: A method for forming a semiconductor device package substrate including a fiducial mark is provided. The method of forming the package substrate includes forming a dielectric layer over a lower portion of the package substrate. A metal layer is formed over a fiducial region of the package substrate. The metal layer is etched to form a first signal line in the fiducial region. A passivation layer is formed over the first signal line. The passivation layer is etched over the first signal line to form a fiducial mark.Type: ApplicationFiled: March 2, 2017Publication date: June 22, 2017Inventor: STEVEN ATHERTON
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Patent number: 9627255Abstract: A method for forming a semiconductor device package substrate including a fiducial mark is provided. The method of forming the package substrate includes forming a dielectric layer over a lower portion of the package substrate. A metal layer is formed over a fiducial region of the package substrate. The metal layer is etched to form a first signal line in the fiducial region. A passivation layer is formed over the first signal line. The passivation layer is etched over the first signal line to form a fiducial mark.Type: GrantFiled: December 10, 2015Date of Patent: April 18, 2017Assignee: NXP USA, INC.Inventor: Steven A. Atherton
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Patent number: 9377504Abstract: A circuit device mounted on a substrate includes a detection circuit that monitors a characteristic of a return signal to determine an integrity of various interconnects of the device.Type: GrantFiled: March 27, 2014Date of Patent: June 28, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Stanley A. Cejka, Steven A. Atherton, William J. Downey, James C. Golab, Brian D. Young
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Publication number: 20150276854Abstract: A circuit device mounted on a substrate includes a detection circuit that monitors a characteristic of a return signal to determine an integrity of various interconnects of the device.Type: ApplicationFiled: March 27, 2014Publication date: October 1, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Stanley A. Cejka, Steven A. Atherton, William J. Downey, James C. Gobab, Brian D. Young