Abstract: A method of controlling the behavior of a latching relay includes receiving a configuration signal of either a first behavior signal or a second behavior signal, receiving a power status signal of either a powered or unpowered signal, receiving either a low-to-high or a high-to-low signal command signal, generating latching pulse in response to receiving a powered signal input as the power status signal and a low-to-high signal as the command signal, generating an unlatching pulse in response to receiving a powered signal input as the power status signal and a high-to-low signal as the command signal input, and generating an unlatching pulse in response to receiving the second behavior signal as the configuration signal and the unpowered signal as the power status signal.

Abstract: A weapon management system includes a management device, interface units, software downloaded into the interface units, a power network, and a communication network. The power network provides electrical power to the management device and the interface units. The communication network connects the management device to the interface units for transferring electrical signals and data between the components. The interface units and the software downloaded into the interface units are highly reconfigurable, allowing for simple, easy, and fast configurability and expandability for evolving weapon systems. Further, the weapon management system has the capability to add interface units to an existing architecture for expanding and evolving weapon systems.

Abstract: A system comprises a first current balancer and a second current balancer. Each of the first and second current balancers includes a first input line for a first voltage source connected to a first output, a second input line for a second voltage source connected to a second output and is in parallel with the first input line, a first series pass element connected in series with the first input line, and a second series pass element connected in series with the second input line. The system further includes a controller operatively connected to the first series pass element and to the second series pass element to throttle at least one of the first series pass element and the second series pass element to balance output current in the first and second outputs.

Abstract: A system includes a first input line for a first voltage source, wherein the first input line is connected to a first output. A second input line is included for a second voltage source, wherein the second input line is connected to a second output and is in parallel with the first input line. A first series pass element is connected in series with the first input line, and a second series pass element is connected in series with the second input line. A controller is operatively connected to the first series pass element and to the second series pass element to throttle at least one of the first series pass element and the second series pass element to balance output current in the first and second outputs.

Abstract: A system includes a first input line for a first voltage source, wherein the first input line is connected to a first output. A second input line is included for a second voltage source, wherein the second input line is connected to a second output and is in parallel with the first input line. A first series pass element is connected in series with the first input line, and a second series pass element is connected in series with the second input line. A controller is operatively connected to the first series pass element and to the second series pass element to throttle at least one of the first series pass element and the second series pass element to balance output current in the first and second outputs.

Abstract: A system comprises a first current balancer and a second current balancer. Each of the first and second current balancers includes a first input line for a first voltage source connected to a first output, a second input line for a second voltage source connected to a second output and is in parallel with the first input line, a first series pass element connected in series with the first input line, and a second series pass element connected in series with the second input line. The system further includes a controller operatively connected to the first series pass element and to the second series pass element to throttle at least one of the first series pass element and the second series pass element to balance output current in the first and second outputs.

Abstract: A linear motor actuator includes a plurality of stators mounted stationary relative to one another along a common actuation axis. A translator rod is mounted to the stators for linear motion relative to the stators along the actuation axis, wherein each stator is magnetically coupled to the translator rod to drive motion of the translator rod along the actuation axis.

Abstract: A system includes a computing system and a cable connector. The computing system includes a plurality of processors and an interconnect circuit configured to connect the plurality of processors to each other. The cable connector is configured to connect to the interconnect circuit and provide a channel identifier to the computing system, and the interconnect circuit is configured to set one of the plurality of processors as a system controller based on the channel identifier.

Abstract: An example actuator control system includes a variable differential transformer (VDT) configured to measure displacement of a motor, and a motor controller configured to control the motor based on displacement data from the VDT. A circuit card assembly (CCA) interconnects the VDT to the motor controller. The CCA includes memory storing configuration data of the VDT, and the CCA is configured to provide the configuration data to the motor controller to calibrate the motor controller for use of the VDT. A method of configuring a motor controller is also disclosed.

Abstract: An example actuator assembly includes an actuator configured to move a rod. A variable differential transformer (VDT) is situated adjacent to the actuator. The VDT includes a core coupled to the rod such that movement of the rod causes a corresponding movement of the core. A plurality of windings surround the core for measuring displacement of the core. A shield surrounds the plurality of windings and shields the plurality of windings from a magnetic field of the actuator. The shield having a maximum permeability of 50,000-500,000. A LVDT configuration method is also disclosed.

Abstract: A method of controlling the behavior of a latching relay includes receiving a configuration signal of either a first behavior signal or a second behavior signal, receiving a power status signal of either a powered or unpowerered signal, receiving either a low-to-high or a high-to-low signal command signal, generating latching pulse in response to receiving a powered signal input as the power status signal and a low-to-high signal as the command signal, generating an unlatching pulse in response to receiving a powered signal input as the power status signal and a high-to-low signal as the command signal input, and generating an unlatching pulse in response to receiving the second behavior signal as the configuration signal and the unpowered signal as the power status signal.

Abstract: A fly-by-wire system includes an electromechanical actuator which includes a plurality of electromechanical motors. Each of the plurality of electromechanical motors is configured and operable to exchange operating status information with the other redundant electromechanical motors within the actuator. Also, each one of the plurality of electromechanical actuators is configured and operable to automatically configure itself for optimal mode of operation based on the received operating status information of at least one of the other electromechanical motors. The fly-by-wire system further includes a flight control computer operatively connected to the plurality of electromechanical motors within the actuator.

Abstract: Systems and methods for command line voting are provided. Aspects include obtaining, by an output logic device, a plurality of memory blocks from a plurality of buffers, each of the plurality of memory blocks including two or more output commands generated from a processing circuit based on a sensor data input, generating, by a hash function, a hash value for each of the plurality of memory blocks, comparing the hash value for each of the plurality of memory blocks to determine an output memory block from the plurality of memory blocks, and outputting, to an output hardware, the two more output commands from the output memory block.

Abstract: A method for testing autonomous reconfiguration logic for an electromechanical actuator includes executing a plurality of test cases against a computer model configured and operable to implement autonomous reconfiguration logic for an electromechanical actuator including a plurality of electromechanical motors to generate a first set of test results. The method further includes executing the plurality of test cases against a programmable logic device configured and operable to implement the autonomous reconfiguration logic for the electromechanical actuator to generate a second set of test results and comparing the first set of test results to the second set of test results.

Abstract: A pulse width modulation signaling system includes a first control channel that is configured to receive a hardware Boolean command input from a first hardware status monitor, receive a software multi-bit command input from a first software system, and generate a first pulse width modulated signal that is representative of the Boolean command input and the software multi-bit command input. The hardware Boolean command input is a binary value of either a first state or a second state, the software multi-bit command input includes a binary value of either a first state or a second state, and the first pulse width modulated signal defines a duty cycle.

Abstract: Embodiments in include a system, a method, and a computer program product for performing intelligent load shedding for multi-channel processing system. The embodiments include a multi-channel processing system, wherein each channel of the multi-channel processing system includes a plurality of processors, and a plurality of links coupling each channel with each other channel in the multi-channel processing system, wherein the links are used to transmit status information of the plurality of processors. The embodiments also include a plurality of cooling elements coupled to each channel having the plurality of processors, wherein the plurality of cooling elements are configured to remove heat from the multi-channel processing system.

Abstract: According to an aspect, a sever system includes a non-volatile storage device with a plurality of loadable configuration data and a configurable sever logic circuit configured responsive to a transfer of the loadable configuration data to perform a plurality of operations. The operations include mapping a plurality of module-level sever logic inputs to a plurality of module-specific sever logic functions as defined in the loadable configuration data. The module-level sever logic inputs are monitored by the configurable sever logic circuit based on the module-specific sever logic functions for a sever condition. A sever command to disconnect one or more outputs of a plurality of modules is triggered based on the module-specific sever logic functions and the module-level sever logic inputs.

Abstract: Systems and methods for command line voting are provided. Aspects include obtaining, by an output logic device, a plurality of memory blocks from a plurality of buffers, each of the plurality of memory blocks including two or more output commands generated from a processing circuit based on a sensor data input, generating, by a hash function, a hash value for each of the plurality of memory blocks, comparing the hash value for each of the plurality of memory blocks to determine an output memory block from the plurality of memory blocks, and outputting, to an output hardware, the two more output commands from the output memory block.

Abstract: According to an aspect, a sever system includes a non-volatile storage device with a plurality of loadable configuration data and a configurable sever logic circuit configured responsive to a transfer of the loadable configuration data to perform a plurality of operations. The operations include mapping a plurality of module-level sever logic inputs to a plurality of module-specific sever logic functions as defined in the loadable configuration data. The module-level sever logic inputs are monitored by the configurable sever logic circuit based on the module-specific sever logic functions for a sever condition. A sever command to disconnect one or more outputs of a plurality of modules is triggered based on the module-specific sever logic functions and the module-level sever logic inputs.

Abstract: A system includes a computing system and a cable connector. The computing system includes a plurality of processors and an interconnect circuit configured to connect the plurality of processors to each other. The cable connector is configured to connect to the interconnect circuit and provide a channel identifier to the computing system, and the interconnect circuit is configured to set one of the plurality of processors as a system controller based on the channel identifier.