Abstract: A method for filling vias with metal includes receiving a substrate having vias, forming a metal plating layer over the vias on a first side of the substrate, fill-plating the vias with a first metal beginning with the metal plating layer on the first side of the substrate and advancing to a second side of the substrate to provide filled vias. The metal plating layer may be subsequently patterned to provide selected circuit connections or chemically-mechanically polished to completely remove the metal plating layer. Forming a metal plating layer over the vias may include filling the vias with a sacrificial filler to enable formation of the metal plating layer and subsequently removing the sacrificial filler via an etching operation or the like. In other embodiments, forming the metal plating layer over the vias is accomplished by bonding a metallic layer onto the first side of the substrate.

Abstract: A method includes storing as communications data at least a portion of received electronic communications, such as emails, that are of interest to user; processing the stored communications data to identify at least one action item that pertains to the user; storing results of the processing including text descriptive of the at least one identified action item in a results repository; and outputting stored results in the results repository to a user device for review by the user. Also disclosed is a computer program product and a system that are configured to implement the method.

Abstract: A method for filling vias with metal includes receiving a substrate having vias, forming a metal plating layer over the vias on a first side of the substrate, fill-plating the vias with a first metal beginning with the metal plating layer on the first side of the substrate and advancing to a second side of the substrate to provide filled vias. The metal plating layer may be subsequently patterned to provide selected circuit connections or chemically-mechanically polished to completely remove the metal plating layer. Forming a metal plating layer over the vias may include filling the vias with a sacrificial filler to enable formation of the metal plating layer and subsequently removing the sacrificial filler via an etching operation or the like. In other embodiments, forming the metal plating layer over the vias is accomplished by bonding a metallic layer onto the first side of the substrate.

Abstract: Resolving a query received from a first node in a network includes accepting, by a second node in the network, ownership of the query from the first node, receiving, at the second node, an identification of a third node in the network, wherein the identification is received from a user of the second node and the user of the second node believes that a user of the third node has information necessary to resolve at least part of the query, and transferring, by the second node, ownership of the at least part of the query to the third node, wherein the accepting, the receiving, and the transferring dynamically generates a data structure that traces a propagation of the query, and the data structure is accessible to an origin of the query.

Abstract: Resolving a query received from a first node in a network includes accepting, by a second node in the network, ownership of the query from the first node, receiving, at the second node, an identification of a third node in the network, wherein the identification is received from a user of the second node and the user of the second node believes that a user of the third node has information necessary to resolve at least part of the query, and transferring, by the second node, ownership of the at least part of the query to the third node, wherein the accepting, the receiving, and the transferring dynamically generates a data structure that traces a propagation of the query, and the data structure is accessible to an origin of the query.

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

Abstract: A method for resolving a query received from a first node in a network includes accepting, by a second node in the network, ownership of the query from the first node, receiving, at the second node, an identification of a third node in the network, wherein the identification is received from a user of the second node and the user of the second node believes that a user of the third node has information necessary to resolve at least part of the query, and transferring, by the second node, ownership of the at least part of the query to the third node, wherein the accepting, the receiving, and the transferring dynamically generates a data structure that traces a propagation of the query, and the data structure is accessible to an origin of the query.

Abstract: The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.

Abstract: According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.

Abstract: Probes are directly patterned on a test substrate, thereby eliminating a need for an interposer. Probe contact structures are formed as a two-level structure having a greater lateral dimension for a lower level portion than for an upper level portion. First cavities are formed in a masking layer applied to a test substrate, filling the cavities with a conductive material, and planarizing the top surfaces of the conductive material portions to form lower level portions. Another masking layer is applied over the lower level portions and patterned to define second cavities having a smaller lateral dimension that the lower level portions. The second cavities are filled with at least one conductive material to form upper level portions of the probe contact structures. The upper level portion of each probe contact structure can be employed to penetrate a surface oxide of solder balls.

Abstract: The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.

Abstract: Probes are directly patterned on a test substrate, thereby eliminating a need for an interposer. Probe contact structures are formed as a two-level structure having a greater lateral dimension for a lower level portion than for an upper level portion. First cavities are formed in a masking layer applied to a test substrate, filling the cavities with a conductive material, and planarizing the top surfaces of the conductive material portions to form lower level portions. Another masking layer is applied over the lower level portions and patterned to define second cavities having a smaller lateral dimension that the lower level portions. The second cavities are filled with at least one conductive material to form upper level portions of the probe contact structures. The upper level portion of each probe contact structure can be employed to penetrate a surface oxide of solder balls.

Abstract: A method for resolving a query received from a first node in a network includes accepting, by a second node in the network, ownership of the query from the first node, receiving, at the second node, an identification of a third node in the network, wherein the identification is received from a user of the second node and the user of the second node believes that a user of the third node has information necessary to resolve at least part of the query, and transferring, by the second node, ownership of the at least part of the query to the third node, wherein the accepting, the receiving, and the transferring dynamically generates a data structure that traces a propagation of the query, and the data structure is accessible to an origin of the query.

Abstract: Resolving a query received from a first node in a network includes accepting, by a second node in the network, ownership of the query from the first node, receiving, at the second node, an identification of a third node in the network, wherein the identification is received from a user of the second node and the user of the second node believes that a user of the third node has information necessary to resolve at least part of the query, and transferring, by the second node, ownership of the at least part of the query to the third node, wherein the accepting, the receiving, and the transferring dynamically generates a data structure that traces a propagation of the query, and the data structure is accessible to an origin of the query.

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

Abstract: Probes are directly patterned on a test substrate, thereby eliminating a need for an interposer. Probe contact structures are formed as a two-level structure having a greater lateral dimension for a lower level portion than for an upper level portion. First cavities are formed in a masking layer applied to a test substrate, filling the cavities with a conductive material, and planarizing the top surfaces of the conductive material portions to form lower level portions. Another masking layer is applied over the lower level portions and patterned to define second cavities having a smaller lateral dimension that the lower level portions. The second cavities are filled with at least one conductive material to form upper level portions of the probe contact structures. The upper level portion of each probe contact structure can be employed to penetrate a surface oxide of solder balls.

Abstract: Probes are directly patterned on a test substrate, thereby eliminating a need for an interposer. Probe contact structures are formed as a two-level structure having a greater lateral dimension for a lower level portion than for an upper level portion. First cavities are formed in a masking layer applied to a test substrate, filling the cavities with a conductive material, and planarizing the top surfaces of the conductive material portions to form lower level portions. Another masking layer is applied over the lower level portions and patterned to define second cavities having a smaller lateral dimension that the lower level portions. The second cavities are filled with at least one conductive material to form upper level portions of the probe contact structures. The upper level portion of each probe contact structure can be employed to penetrate a surface oxide of solder balls.

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

Abstract: The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

Abstract: The present invention allows for direct chip-to-chip connections using the shortest possible signal path.