Patents by Inventor Steven A. Cordes
Steven A. Cordes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9270739Abstract: Resolving a query received from a first node in a network includes accepting, by a second node in the network, ownership of the query from the first node, receiving, at the second node, an identification of a third node in the network, wherein the identification is received from a user of the second node and the user of the second node believes that a user of the third node has information necessary to resolve at least part of the query, and transferring, by the second node, ownership of the at least part of the query to the third node, wherein the accepting, the receiving, and the transferring dynamically generates a data structure that traces a propagation of the query, and the data structure is accessible to an origin of the query.Type: GrantFiled: August 19, 2013Date of Patent: February 23, 2016Assignee: International Business Machines CorporationInventors: Steven A. Cordes, Debra C. Leach, Debra A. Loussedes, Patrick R. Varekamp
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Patent number: 9263292Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.Type: GrantFiled: December 5, 2013Date of Patent: February 16, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Guy M. Cohen, Steven A. Cordes, Sherif A. Goma, Joanna Rosner, Jeannine M. Trewhella
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Patent number: 9258356Abstract: A method for resolving a query received from a first node in a network includes accepting, by a second node in the network, ownership of the query from the first node, receiving, at the second node, an identification of a third node in the network, wherein the identification is received from a user of the second node and the user of the second node believes that a user of the third node has information necessary to resolve at least part of the query, and transferring, by the second node, ownership of the at least part of the query to the third node, wherein the accepting, the receiving, and the transferring dynamically generates a data structure that traces a propagation of the query, and the data structure is accessible to an origin of the query.Type: GrantFiled: March 12, 2013Date of Patent: February 9, 2016Assignee: International Business Machines CorporationInventors: Steven A. Cordes, Debra C. Leach, Debra A. Loussedes, Patrick R. Varekamp
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Patent number: 9171742Abstract: The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.Type: GrantFiled: July 22, 2013Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES U.S. 2 LLCInventors: Evan G. Colgan, Steven A. Cordes, Daniel C. Edelstein, Vijayeshwar D. Khanna, Kenneth Latzko, Qinghuang Lin, Peter J. Sorce, Sri M. Sri-Jayantha, Robert L. Wisnieff, Roy R. Yu
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Publication number: 20150285998Abstract: According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.Type: ApplicationFiled: April 2, 2014Publication date: October 8, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Aydin Babakhani, Steven A. Cordes, Jean-Olivier Plouchart, Scott K. Reynolds, Peter J. Sorce, Robert E. Trzcinski
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Patent number: 9057741Abstract: Probes are directly patterned on a test substrate, thereby eliminating a need for an interposer. Probe contact structures are formed as a two-level structure having a greater lateral dimension for a lower level portion than for an upper level portion. First cavities are formed in a masking layer applied to a test substrate, filling the cavities with a conductive material, and planarizing the top surfaces of the conductive material portions to form lower level portions. Another masking layer is applied over the lower level portions and patterned to define second cavities having a smaller lateral dimension that the lower level portions. The second cavities are filled with at least one conductive material to form upper level portions of the probe contact structures. The upper level portion of each probe contact structure can be employed to penetrate a surface oxide of solder balls.Type: GrantFiled: July 20, 2012Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: David M. Audette, Kevin Bocash, S. Jay Chey, Steven A. Cordes, Dustin M. Fregeau
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Publication number: 20150024549Abstract: The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.Type: ApplicationFiled: July 22, 2013Publication date: January 22, 2015Applicant: International Business Machines CorporationInventors: Evan G. Colgan, Steven A. Cordes, Daniel C. Edelstein, Vijayeshwar D. Khanna, Kenneth Latzko, Qinghuang Lin, Peter J. Sorce, Sri M. Sri-Jayantha, Robert L. Wisnieff, Roy R. Yu
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Patent number: 8933717Abstract: Probes are directly patterned on a test substrate, thereby eliminating a need for an interposer. Probe contact structures are formed as a two-level structure having a greater lateral dimension for a lower level portion than for an upper level portion. First cavities are formed in a masking layer applied to a test substrate, filling the cavities with a conductive material, and planarizing the top surfaces of the conductive material portions to form lower level portions. Another masking layer is applied over the lower level portions and patterned to define second cavities having a smaller lateral dimension that the lower level portions. The second cavities are filled with at least one conductive material to form upper level portions of the probe contact structures. The upper level portion of each probe contact structure can be employed to penetrate a surface oxide of solder balls.Type: GrantFiled: June 21, 2012Date of Patent: January 13, 2015Assignee: International Business Machines CorporationInventors: David M. Audette, Kevin Bocash, S. Jay Chey, Steven A. Cordes, Dustin M. Fregeau
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Publication number: 20140280027Abstract: Resolving a query received from a first node in a network includes accepting, by a second node in the network, ownership of the query from the first node, receiving, at the second node, an identification of a third node in the network, wherein the identification is received from a user of the second node and the user of the second node believes that a user of the third node has information necessary to resolve at least part of the query, and transferring, by the second node, ownership of the at least part of the query to the third node, wherein the accepting, the receiving, and the transferring dynamically generates a data structure that traces a propagation of the query, and the data structure is accessible to an origin of the query.Type: ApplicationFiled: August 19, 2013Publication date: September 18, 2014Applicant: International Business Machines CorporationInventors: Steven A. Cordes, Debra C. Leach, Debra A. Loussedes, Patrick R. Varekamp
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Publication number: 20140280449Abstract: A method for resolving a query received from a first node in a network includes accepting, by a second node in the network, ownership of the query from the first node, receiving, at the second node, an identification of a third node in the network, wherein the identification is received from a user of the second node and the user of the second node believes that a user of the third node has information necessary to resolve at least part of the query, and transferring, by the second node, ownership of the at least part of the query to the third node, wherein the accepting, the receiving, and the transferring dynamically generates a data structure that traces a propagation of the query, and the data structure is accessible to an origin of the query.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: International Business Machines CorporationInventors: Steven A. Cordes, Debra C. Leach, Debra A. Loussedes, Patrick R. Varekamp
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Publication number: 20140141618Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.Type: ApplicationFiled: December 5, 2013Publication date: May 22, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Guy M. Cohen, Steven A. Cordes, Sherif A. Goma, Joanna Rosner, Jeannine M. Trewhella
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Publication number: 20130344694Abstract: Probes are directly patterned on a test substrate, thereby eliminating a need for an interposer. Probe contact structures are formed as a two-level structure having a greater lateral dimension for a lower level portion than for an upper level portion. First cavities are formed in a masking layer applied to a test substrate, filling the cavities with a conductive material, and planarizing the top surfaces of the conductive material portions to form lower level portions. Another masking layer is applied over the lower level portions and patterned to define second cavities having a smaller lateral dimension that the lower level portions. The second cavities are filled with at least one conductive material to form upper level portions of the probe contact structures. The upper level portion of each probe contact structure can be employed to penetrate a surface oxide of solder balls.Type: ApplicationFiled: July 20, 2012Publication date: December 26, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David M. Audette, Kevin Bocash, S. Jay Chey, Steven A. Cordes, Dustin M. Fregeau
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Patent number: 8603846Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.Type: GrantFiled: February 10, 2011Date of Patent: December 10, 2013Assignee: International Business Machines CorporationInventors: Guy A. Cohen, Steven A. Cordes, Sherif A. Goma, Joanna Rosner, Jeannine M. Trewhella
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Patent number: 8551816Abstract: The present invention allows for direct chip-to-chip connections using the shortest possible signal path.Type: GrantFiled: April 4, 2012Date of Patent: October 8, 2013Assignee: International Business Machines CorporationInventors: Steven A. Cordes, Matthew J. Farinelli, Sherif A. Goma, Peter A. Gruber, John U. Knickerbocker, James L. Speidell
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Patent number: 8237271Abstract: The present invention allows for direct chip-to-chip connections using the shortest possible signal path.Type: GrantFiled: June 19, 2007Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Steven A. Cordes, Matthew J. Farinelli, Sherif A. Goma, Peter A. Gruber, John U. Knickerbocker, James L. Speidell
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Publication number: 20120187577Abstract: The present invention allows for direct chip-to-chip connections using the shortest possible signal path.Type: ApplicationFiled: April 4, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven A. Cordes, Matthew J. Farinelli, Sherif A. Goma, Peter A. Gruber, John U. Knickerbocker, James L. Speidell
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Patent number: 8159248Abstract: Flexible and rigid interposers for use in the semiconductor industry and methods for manufacturing the same are described. Auto-catalytic processes are used to minimize the costs associated with the production of flexible interposers, while increasing the yield and lifetime. Electrical contact regions are easily isolated and the risk of corrosion is reduced because all portions of the interposer are plated at once. Leads projecting from the flexible portion of the interposers accommodate a greater variety of components to be tested. Rigid interposers include a pin projecting from a probe pad affixed to a substrate. The rigidity of the pin penetrates oxides on a contact pad to be tested. Readily available semiconductor materials and processes are used to manufacture the flexible and rigid interposers according to the invention. The flexible and rigid interposers can accommodate pitches down to 25 ?m.Type: GrantFiled: August 18, 2009Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Steven A. Cordes, Matthew J. Farinelli, Sherif A. Goma
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Publication number: 20110130005Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.Type: ApplicationFiled: February 10, 2011Publication date: June 2, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Guy A. Cohen, Steven A. Cordes, Sherif A. Goma, Joanna Rosner, Jeannine M. Trewhella
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Patent number: 7915064Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.Type: GrantFiled: August 10, 2009Date of Patent: March 29, 2011Assignee: International Business Machines CorporationInventors: Guy A. Cohen, Steven A. Cordes, Sherif A. Goma, Joanna Rosner, Jeannine M. Trewhella
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Patent number: 7810702Abstract: A method of producing standoffs in an injection molded solder (IMS) mold, which possesses cavities, each of which is filled with a solder paste using standard techniques, such as screening or IMS. This solder paste is heated to a reflow temperature at which the solder melts and forms a ball or sphere. Since solder pastes are known to reduce in volume due to the therein contained organic material burning off, the remaining solder ball will be significantly lower in volume than that of the cavity. A solder material having a lower melting point is then filled into the cavities about the solder balls. The mold and solder metal are then allowed to cool, resulting in the formation of a solid sphere of metal in the cavity surrounded by solder material of a lower melting point, which, upon transfer to a wafer, form the standoffs.Type: GrantFiled: July 2, 2008Date of Patent: October 12, 2010Assignee: International Business Machines CorporationInventors: Steven A. Cordes, Peter A. Gruber