Abstract: A method and apparatus for a circuit physically realizing a CMOS buffer with a controlled slew rate at the output and using no additional standby power to achieve the slew rate control is described. A feedback path from the output is coupled to transistors comprising a differential pair, the transistors are further coupled to a capacitance. The discharge rate of the capacitance and the size choices of the transistors in the circuit are used with the feedback path to control the high-to-low and low-to-high transition rate of the output. The circuit of the invention allows a system designer to construct a buffer for driving a bus with excellent on chip and bus signal noise characteristics using standard digital CMOS technology and having excellent standby and active power characteristics. An open drain buffer and a push-pull buffer are described. An integrated circuit implementing application logic coupled to input/output and output buffers embodying this circuit is disclosed.

Abstract: A method and apparatus for a circuit physically realizing a CMOS buffer with a controlled slew rate at the output and using no additional standby power to achieve the slew rate control is described. A feedback path from the output is coupled to transistors comprising a differential pair, the transistors are further coupled to a capacitance. The discharge rate of the capacitance and the size choices of the transistors in the circuit are used with the feedback path to control the high-to-low and low-to high transition rate of the output. The circuit of the invention allows a system designer to construct a buffer for driving a bus with excellent on chip and bus signal noise characteristics using standard digital CMOS technology and having excellent standby and active power characteristics. An open drain buffer and a push-pull buffer are described. An integrated circuit implementing application logic coupled to input/output and output buffers embodying this circuit is disclosed.

Abstract: An improved buffer circuit with a low-pass filter includes a first variable resistance which forms the input of the buffer circuit and is connected to a clamp circuit, a variable capacitor, a second variable resistance, a third variable resistance, and a buffer. A first compensation circuit is connected between the buffer and the second variable resistance. A second compensation circuit is connected between the buffer and the third variable resistance. First and second compensation circuits provide feedback paths through the second and third variable resistances which enable the voltage at the node connecting the first variable resistance, the clamp circuit, the variable capacitor, and the buffer to be "pulled up" or "pulled down" depending upon the signal transition at the input thereby following the node voltage a the buffer circuit input more quickly thus reducing recovery time and allowing the buffer circuit to concurrently filter noise and increase switching frequency.

Abstract: A temperature compensation circuit (FIG. 5a) has a controlled temperature compensated voltage drop across R1. A Schottky diode D1 is connected to the base of Q1 through resistor R1. The temperature coefficients of the base-emitter junction of Q1 and the diode D1 have a predetermined differential, preferably none. The forward voltage drop across D1 and the base-emitter junction are different, thereby establishing a controlled current through resistor R1 that is independent of temperature.