Abstract: An apparatus for generating structured illumination images, comprising a housing; imaging optics mounted within the housing, the imaging optics configured to focus illumination from an illumination source such that an in-focus pattern of light corresponding to a pattern on a photomask is projected onto a sample; a reflector mounted within the housing and configured to reflect the illumination to a sample; a filter apparatus, comprising one or more filters mounted within the housing, the filter apparatus configured to allow only emissions from the illuminated sample to pass through to the sensor; and mounting features on the housing, the mounting features configured to allow the apparatus to be installed within an imaging system.

Abstract: A method for calibrating an imaging system can include at least the following method acts: illuminating a sample through a pinhole mask using an excitation light; capturing an image of the sample using a sensor; converting the image into data; in a processing module: filtering the data using a known spacing of pinholes in the pinhole mask to obtain filtered data that corresponds to the known spacing, using a threshold to identify regions of the filtered data that are bright enough to be associated with a pinhole, calculating the centroids of the regions, and fitting a known pattern for the pinhole mask to the regions in order to identify the best fit data for the filtered data; and storing, in a storage medium, the best fit data for use in a subsequent confocal capture routine.

Abstract: A method for generating a composite image obtained in a fluorescence imaging system, comprising: determining the physical locations of a pinhole mask relative to a sample required to construct a full composite confocal image; generating in a control module a randomized order for the determined physical locations; moving the photomask or the sample to the determined physical locations in the randomized order under control of the control module and using a translation stage; illuminating the sample through the photomask using an excitation light; capturing a plurality of images at each of the physical locations using a sensor in order to generate a set of data points; using the randomized order to generate a composite image based on the set of data points and measuring the brightness of at least some of the data points; and adjusting the brightness of some of the set of data points.

Abstract: A method for calibrating an imaging system, comprising: illuminating a sample through a pinhole mask using an excitation light; capturing an image of the sample using a sensor; converting the image into data; in a processing module: filtering the data using known spacing of pinholes in the pinhole mask to obtain data that corresponds to the spacing, using a threshold to identify regions of the remaining data that are bright enough to be associated with a pinhole, calculating the centroids of the regions, and fitting a known pattern for the pinhole mask to the regions in order to identify the best fit for the data; and storing, in a storage medium, the best fit data for use in a subsequent confocal capture routine.

Abstract: A method for generating a composite image obtained in a fluorescence imaging system, comprising: determining the physical locations of a pinhole mask relative to a sample required to construct a full composite confocal image; generating in a control module a randomized order for the determined physical locations; moving the photomask or the sample to the determined physical locations in the randomized order under control of the control module and using a translation stage; illuminating the sample through the photomask using an excitation light; capturing a plurality of images at each of the physical locations using a sensor in order to generate a set of data points; using the randomized order to generate a composite image based on the set of data points and measuring the brightness of at least some of the data points; and adjusting the brightness of some of the set of data points.

Abstract: An apparatus for generating structured illumination images, comprising a housing; imaging optics mounted within the housing, the imaging optics configured to focus illumination from an illumination source such that an in-focus pattern of light corresponding to a pattern on a photomask is projected onto a sample; a reflector mounted within the housing and configured to reflect the illumination to a sample; a filter apparatus, comprising one or more filters mounted within the housing, the filter apparatus configured to allow only emissions from the illuminated sample to pass through to the sensor; and mounting features on the housing, the mounting features configured to allow the apparatus to be installed within an imaging system.

Abstract: Embodiments relate to systems and methods for sample image capture using integrated control. A digital microscope or other imaging device can be associated with a sample chamber containing cell, tissue, or other sample material. The chamber can be configured to operate using a variety of environmental variables, including gas concentration, temperature, humidity, and others. The imaging device can be configured to operate using a variety of imaging variables, including magnification, focal length, illumination, and others. A central system control module can be used to configure the settings of those hardware elements, as well as others, to set up and carry out an image capture event. The system control module can be operated to control the physical, optical, chemical, and/or other parameters of the overall imaging environment from one central control point. The variables used to produce the image capture can be configured to dynamically variable during the media capture event.

Abstract: In accordance with the invention, there are electron beam inspection systems, electron beam testable semiconductor test structures, and methods for detecting systematic defects, such as, for example contact-to-gate shorts, worm hole leakage paths, holes printing issues, and anomalies in sparse holes and random defects, such as, current leakage paths due to dislocations and pipes during semiconductor processing.

Abstract: An illumination system for a fluorescence microscope is provided. The illumination system includes a carriage removably receivable within the microscope and a plurality of filter cubes movably arranged on the carriage, wherein each filter cube is moveable between an active position and an inactive position. Each filter cube includes a housing having first and second openings and a solid state light source secured to the housing. The solid state light source emits light when the filter cube is moved into the active position. Each filter cube further comprises at least one optical filter disposed within the housing, wherein the optical filter corresponds to the solid state light source.

Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.

Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.

Abstract: The present invention provides a method of forming integrated circuit interconnect structures wherein a passing metal feature does not include a landing pad. In an exemplary embodiment, the method includes forming a via opening through first and second dielectric layers, such as silicon dioxide layer, located over a conductive layer, such as copper, and to a first etch stop layer, such as silicon nitride, located over the conductive layer. A trench opening is then formed through the second dielectric layer and to a second etch stop layer. Once the via and trench openings are formed, an etch is conducted that etches through the first etch stop layer such that the opening contacts the underlying conductive layer.

Abstract: The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and photodefining a trench, etching the hard mask and partially etching the dielectric to form a trench having a bottom, stripping the photoresist, applying a second photoresist and photodefining a slit across the trench, selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Later, a connection to the underlying metal is formed and integrated circuits made thereby.

Abstract: The present invention provides a semiconductor device and method of manufacture thereof that provides improved dielectric thickness control. The semiconductor device includes a metal feature located on a semiconductor substrate, wherein the metal feature has openings formed therein, or depending on the device, therethrough. The semiconductor device further includes a fluorinated dielectric layer located over the metal feature and within the openings. Thus, the inclusion of openings within the metal feature allows for a substantially planar surface of the fluorinated dielectric layer.

Abstract: A method for stripping photoresist material (26) from a semiconductor substrate (16) avoids incorporation of sodium and other contaminant ions from a rework solvent. An oxygen and hydrogen plasma mixture strips the photoresist material without significant introduction of oxygen into the titanium nitride layer (24). Any oxidation of the titanium nitride is reversed by exposing the substrate to an oxygen-free, reducing plasma, such as a hydrogen-containing plasma. The titanium nitride layer is thereby much less susceptible to incorporation of contaminant ions in a subsequent cleaning with rework solvent than a layer which has been extensively oxidized during the plasma stripping process.

Abstract: An integrated circuit having one or more antifuses which connect electrical components through a dielectric layer. The antifuse is formed before the thick dielectric is deposited and patterned to form windows which expose the antifuse.