Patents by Inventor Steven A. Michaelson

Steven A. Michaelson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240115621
    Abstract: The present application is directed to the field of implants comprising soft tissue for use in implantation in humans. The soft tissue implants of the present application are preferably obtained from xenograft sources. The present application provides a chemical process that sterilizes, removes antigens from and/or strengthens xenograft implants. The present techniques yield soft tissue implants having superior structural, mechanical, and/or biochemical integrity. The present application is also directed to processes for treating xenograft implants comprising soft tissues such as dermis, and to implants produced by such processes.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 11, 2024
    Applicant: Tutogen Medical GmbH
    Inventors: Arnd Wilhelmi, Silke Schreiner, Jake Michaelson, Steven Moore, Jennifer Faleris, Anne Reinlein
  • Patent number: 6499118
    Abstract: A method of determining a redundancy solution for a semiconductor memory under test (DUT) having redundant rows and columns is disclosed. The method includes the steps of first testing the DUT in a first environment with a first tester to generate a first fail data set. The first fail data set is then transferred to a second tester where the DUT is test in a second environment to generate a second fail data set. The first and second failure data sets are then merged to create a merged fail data set. A highly optimized redundancy solution is then determined based on the merged fail data set.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: December 24, 2002
    Assignee: Teradyne, Inc.
    Inventor: Steven A. Michaelson
  • Patent number: 5795797
    Abstract: A process for manufacturing semiconductor memories which includes a method of quickly and effectively identifying which faulty memory cells are to be replaced by redundant memory structures. Redundant rows and columns are assigned to replace rows and columns with faulty cells in an iterative process. At each pass, one row or column is identified for replacement. A row or column is selected for replacement based on priorities assigned to the faulty cells within the rows and columns. The highest priority cell for a row is the one in a column with the fewest other faulty cells. Where multiple cells have the same highest row priority, the cell in a row with the most faulty cells is given a higher priority. A similar dual measure is used for assigning column priorities to cells. Once a highest priority row and column are identified, the single element with the highest priority is identified.
    Type: Grant
    Filed: August 18, 1995
    Date of Patent: August 18, 1998
    Assignee: Teradyne, Inc.
    Inventors: Michael A. Chester, Steven A. Michaelson
  • Patent number: 5754556
    Abstract: A semiconductor memory manufacturing system including a tester sub-system and a redundancy analysis sub-system. The manufacturing system includes a transfer circuit between the test sub-system and the redundancy analysis sub-system that reduces the number of bits of data transferred to the redundancy analyzer. This speeds up the transfer process and also speeds up the redundancy analysis.
    Type: Grant
    Filed: July 18, 1996
    Date of Patent: May 19, 1998
    Assignee: Teradyne, Inc.
    Inventors: Steve G. Ramseyer, Steven A. Michaelson, Michael H. Augarten