Patents by Inventor Steven A. Peterson

Steven A. Peterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8982999
    Abstract: An embodiment of the invention includes a receiver with reduced error terms and incoming jitter tracking that improves jitter tolerance. An embodiment provides these benefits based on a voltage integrator that recovers data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. An embodiment provides these benefits based on a time integrator that recovers, using digital logic, data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. Other embodiments are described herein.
    Type: Grant
    Filed: September 30, 2012
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventors: Kiriti Bhagavathula, Chunyu Zhang, Steven A. Peterson
  • Publication number: 20140368667
    Abstract: Apparatus, methods, and systems are herein described for providing a method for calibrating a channel by employing a training sequence during at least one blanking interval. In one embodiment, an apparatus includes a first control logic to send a command to generate a predetermined data pattern during at least one blanking interval. In addition, the apparatus includes a second control logic to determine whether a received data pattern matches the predetermined data pattern.
    Type: Application
    Filed: December 29, 2013
    Publication date: December 18, 2014
    Inventors: Steven A. Peterson, Haran Thanigasalam, Sriram Balasubrahmanyam
  • Publication number: 20140092951
    Abstract: An embodiment of the invention includes a receiver with reduced error terms and incoming jitter tracking that improves jitter tolerance. An embodiment provides these benefits based on a voltage integrator that recovers data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. An embodiment provides these benefits based on a time integrator that recovers, using digital logic, data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. Other embodiments are described herein.
    Type: Application
    Filed: September 30, 2012
    Publication date: April 3, 2014
    Inventors: Kiriti Bhagavathula, Chunyu Zhang, Steven A. Peterson
  • Patent number: 7161851
    Abstract: A system and method for generating multiple drive strengths for one or more output signals of a memory controller operable to control a memory subsystem. The system includes a state machine operable to generate an n-bit output representative of a drive strength operable to drive the one or more output signals; and a plurality of adders, each adder having a plurality of n-bit inputs, each input receiving a selective set of bits from the n-bit output of the state machine, the adders generating a plurality of n-bit outputs representative of drive strengths operable to drive the output signals. The method includes generating an n-bit output representative of a drive strength, and adding combinations of two or more selective sets of bits from the n-bit output to generate a plurality of n-bit outputs representative of a plurality of drive strengths that are operable to drive the output signal.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: January 9, 2007
    Assignee: Intel Corporation
    Inventors: Steven A. Peterson, Razi Uddin, Vishal Sharma
  • Patent number: 6756810
    Abstract: A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated based on matching an internal impedance generated by transistors with an impedance of the external impedance element, and then the reference impedance code can be shifted to generate new impedance codes according to impedance requirements of various different circuits that require compensation. Use of the single external impedance element for compensation of multiple circuits reduces motherboard and packaging costs. Chip area is also conserved since simpler compensation circuits can be used.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: June 29, 2004
    Assignee: Intel Corporation
    Inventors: Usman A. Mughal, Razi Uddin, Chee How Lim, Steven A. Peterson
  • Publication number: 20030128596
    Abstract: A system and method for generating multiple drive strengths for one or more output signals of a memory controller operable to control a memory subsystem. The system includes a state machine operable to generate an n-bit output representative of a drive strength operable to drive the one or more output signals; and a plurality of adders, each adder having a plurality of n-bit inputs, each input receiving a selective set of bits from the n-bit output of the state machine, the adders generating a plurality of n-bit outputs representative of drive strengths operable to drive the output signals. The method includes generating an n-bit output representative of a drive strength, and adding combinations of two or more selective sets of bits from the n-bit output to generate a plurality of n-bit outputs representative of a plurality of drive strengths that are operable to drive the output signal.
    Type: Application
    Filed: January 7, 2002
    Publication date: July 10, 2003
    Inventors: Steven A. Peterson, Razi Uddin, Vishal Sharma
  • Publication number: 20030112050
    Abstract: A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated based on matching an internal impedance generated by transistors with an impedance of the external impedance element, and then the reference impedance code can be shifted to generate new impedance codes according to impedance requirements of various different circuits that require compensation. Use of the single external impedance element for compensation of multiple circuits reduces motherboard and packaging costs. Chip area is also conserved since simpler compensation circuits can be used.
    Type: Application
    Filed: February 6, 2003
    Publication date: June 19, 2003
    Inventors: Usman A. Mughal, Razi Uddin, Chee How Lim, Steven A. Peterson
  • Patent number: 6545522
    Abstract: A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated based on matching an internal impedance generated by transistors with an impedance of the external impedance element, and then the reference impedance code can be shifted to generate new impedance codes according to impedance requirements of various different circuits that require compensation. Use of the single external impedance element for compensation of multiple circuits reduces motherboard and packaging costs. Chip area is also conserved since simpler compensation circuits can be used.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: April 8, 2003
    Assignee: Intel Corporation
    Inventors: Usman A. Mughal, Razi Uddin, Chee How Lim, Steven A. Peterson
  • Publication number: 20020172066
    Abstract: A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated based on matching an internal impedance generated by transistors with an impedance of the external impedance element, and then the reference impedance code can be shifted to generate new impedance codes according to impedance requirements of various different circuits that require compensation. Use of the single external impedance element for compensation of multiple circuits reduces motherboard and packaging costs. Chip area is also conserved since simpler compensation circuits can be used.
    Type: Application
    Filed: May 17, 2001
    Publication date: November 21, 2002
    Inventors: Usman A. Mughal, Razi Uddin, Chee How Lim, Steven A. Peterson