Abstract: Apparatus, circuits, systems, and associated methods for integrating SAS/STP control in a SATA storage device. Features and aspects hereof permit direct coupling of the SATA storage device to either a SATA host or to an STP initiator without requiring an intervening SAS expander.

Abstract: A packetized data bus interface may be placed in a mode where data packets may be transmitted that are much larger than the standard packet size. The mode may allow the interface device and any other devices, networks, or transmission lines attached to the interface device to be more thoroughly exercised than previously able. The mode may be used for characterizing various aspects of the data interface.

Abstract: An elasticity buffer has a reset input that, when activated, causes the elasticity buffer to temporarily cease operation. When the reset input bit is released, the elasticity buffer may resume operation. During periods when a device on a serial bus may be halted for power saving mode, for example, the serial communication may be reestablished and then the elasticity buffer may be released to continue operation.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to store input data in response to a write pointer and present output data in response to a read pointer. The second circuit may be configured to generate a control signal in response to the write pointer, the read pointer and a type of an information packet containing the input data.

Abstract: Apparatus, circuits, systems, and associated methods for integrating SAS/STP control in a SATA storage device. Features and aspects hereof permit direct coupling of the SATA storage device to either a SATA host or to an STP initiator without requiring an intervening SAS expander.

Abstract: An apparatus comprising one or more user programmable registers and a circuit configured to compare a predetermined portion of one or more information packets with contents of said one or more user programmable registers.

Abstract: An apparatus generally comprising a plurality of writeable registers, a control circuit, and a transmitter circuit. The writeable registers may be configured to store (i) a first burst value and (ii) a first gap value. The control circuit may be configured to generate an idle signal (i) in a transmit state for a first duration determined by the first burst value and (ii) in an idle state for a second duration determined by the first gap value in response to a first command signal. The transmitter circuit may be configured to (i) enable transmitting while the idle signal is in the transmit state and (ii) disable transmitting while the idle signal is in the idle state.

Abstract: A circuit generally comprising a first circuit and a second circuit. The first circuit may be configured to (i) detect a state of an input signal and (ii) present a plurality of intermediate signals each representative of the state of the input signal during a plurality of clock cycles. The second circuit may be configured to present a filtered signal in response to a selected number of the intermediate signals having a predetermined state.

Abstract: A system generally having a first circuit, a second circuit, and a pair of non-crossing conductive paths. The first circuit may be configured to convert between (i) a serial signal on a first differential interface and (ii) a parallel signal. The pair of non-crossing conductive paths may connect the first differential interface with a second differential interface. The second circuit may be configured to invert the parallel signal in response to a control signal in an inverting state.

Abstract: An elasticity buffer has a reset input that, when activated, causes the elasticity buffer to temporarily cease operation. When the reset input bit is released, the elasticity buffer may resume operation. During periods when a device on a serial bus may be halted for power saving mode, for example, the serial communication may be reestablished and then the elasticity buffer may be released to continue operation.

Abstract: A packetized data bus interface may be placed in a mode where data packets may be transmitted that are much larger than the standard packet size. The mode may allow the interface device and any other devices, networks, or transmission lines attached to the interface device to be more thoroughly exercised than previously able. The mode may be used for characterizing various aspects of the data interface.

Abstract: An apparatus comprising one or more user programmable registers and a circuit configured to compare a predetermined portion of one or more information packets with contents of said one or more user programmable registers.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to store input data in response to a write pointer and present output data in response to a read pointer. The second circuit may be configured to generate a control signal in response to the write pointer, the read pointer and a type of an information packet containing the input data.

Abstract: An order in which bits for serial data are transmitted or received by a first device, integrated circuit (IC) or logic, is programmable to be either from most significant bit (MSB) to least significant bit (LSB) or from LSB to MSB. Therefore, when the first device is used with a second device, integrated circuit (IC) or logic, which can handle the serial data in only one order, the first device is programmed, or configured, to handle the serial data in the same order as the second device.

Abstract: A built-in test for dynamic raster video output is described for testing a plurality of analog video signals created from digital raster data, each of the analog signals having a plurality of analog signal components. In the apparatus, an addressing device is provided for selecting one of the analog signals to be tested, and a selector selects a desired analog signal component from the selected analog signal. An A/D converter then converts the selected signal component into a digital signal component, and a characteristic value is extracted therefrom. A memory is provided which stores predetermined characteristic value range data, and the extracted characteristic value is compared with the stored range data by a comparator to produce a result. A combination device then creates a combination of the result and an address of the selected analog signal component, and the combination is then stored for later retrieval.