Abstract: Methods and apparatus for preprocessing commands by a data transfer device. A prefetch processor creates a list of contiguous pointers in a local memory coupled to a controller CPU, based on pointers stored by a host processing system coupled to the data transfer device. When the controller CPU is ready to execute a command, it uses the pointer list in the local memory to determine where to transfer data associated with the command.

Abstract: A method and apparatus for reducing the time for rebuilding a memory mapping table in a host computer. A memory mapping table is maintained by a host computer in dynamic memory and duplicated in a data storage device, for example, a solid state drive (SSD). If power is lost, a rebuild engine inside the data storage device separate and apart from a controller CPU rebuilds the memory mapping table in the dynamic memory based on a copy of the memory mapping table maintained by the data storage device.

Abstract: Methods and apparatus are described to dynamically adjust internal resources and arbitration schemes of a block I/O device that allows for efficient bandwidth utilization and increased IO performance of the block I/O device. Commands from a plurality of hosts are monitored and measured under various workloads, and the block I/O device dynamically adjusts internal resources and arbitration schemes based on the received commands.

Abstract: A system, method and apparatus for encrypting data. A host processor and host memory are coupled to a block I/O device. The host processor issues encryption and decryption commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device performs encryption on data specified in the encryption command, thus relieving the host processor of performing the encryption and freeing the host processor for other tasks.

Abstract: A system, method and apparatus for compressing and decompressing data. A host processor and host memory are coupled to a block I/O device. The host processor issues compress and decompress commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device compresses/decompresses the data specified in the compress/decompress command, thus relieving the host processor of performing the compression/decompression and freeing the host processor for other tasks.

Abstract: A system, method and apparatus for encoding and decoding data. A host processor and host memory are coupled to a block I/O device. The host processor issues encode and decode commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device encodes the data specified in the encode command, thus relieving the host processor of performing the encoding/decoding and freeing the host processor for other tasks.

Abstract: A system, method and apparatus for encrypting data. A host processor and host memory are coupled to a block I/O device. The host processor issues encryption and decryption commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device performs encryption on data specified in the encryption command, thus relieving the host processor of performing the encryption and freeing the host processor for other tasks.

Abstract: A system, method and apparatus for encoding and decoding data. A host processor and host memory are coupled to a block I/O device. The host processor issues encode and decode commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device encodes the data specified in the encode command, thus relieving the host processor of performing the encoding/decoding and freeing the host processor for other tasks.

Abstract: A system, method and apparatus for compressing and decompressing data. A host processor and host memory are coupled to a block I/O device. The host processor issues compress and decompress commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device compresses/decompresses the data specified in the compress/decompress command, thus relieving the host processor of performing the compression/decompression and freeing the host processor for other tasks.

Abstract: A system, method and apparatus for encrypting data. A host processor and host memory are coupled to a block I/O device. The host processor issues encryption and decryption commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device performs encryption on data specified in the encryption command, thus relieving the host processor of performing the encryption and freeing the host processor for other tasks.

Abstract: Apparatus, circuits, systems, and associated methods for integrating SAS/STP control in a SATA storage device. Features and aspects hereof permit direct coupling of the SATA storage device to either a SATA host or to an STP initiator without requiring an intervening SAS expander.

Abstract: Described embodiments provide for switching from a low-power mode of a device such as, for example, a SAS or SATA receiver, to an active mode. The device enters the low-power mode by shutting down i) logic devices of a physical layer of the device and ii) a decoding circuit of the device. Activity at an input of a receiver of the device is detected while in low-power mode, and the device switches, in response to the detected activity, from the low-power mode to the active mode by powering up i) the logic devices of the physical layer and ii) the decoding circuit when activity is detected, thereby responding to the detected activity as if it is a predetermined command.

Abstract: A packetized data bus interface may be placed in a mode where data packets may be transmitted that are much larger than the standard packet size. The mode may allow the interface device and any other devices, networks, or transmission lines attached to the interface device to be more thoroughly exercised than previously able. The mode may be used for characterizing various aspects of the data interface.

Abstract: An elasticity buffer has a reset input that, when activated, causes the elasticity buffer to temporarily cease operation. When the reset input bit is released, the elasticity buffer may resume operation. During periods when a device on a serial bus may be halted for power saving mode, for example, the serial communication may be reestablished and then the elasticity buffer may be released to continue operation.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to store input data in response to a write pointer and present output data in response to a read pointer. The second circuit may be configured to generate a control signal in response to the write pointer, the read pointer and a type of an information packet containing the input data.

Abstract: Apparatus, circuits, systems, and associated methods for integrating SAS/STP control in a SATA storage device. Features and aspects hereof permit direct coupling of the SATA storage device to either a SATA host or to an STP initiator without requiring an intervening SAS expander.

Abstract: A high speed, two-way serial interface with a scrambler and de-scrambler may be tested by sending a single word repeatedly through the scrambler to create a pseudo-random sequence. The pseudo-random sequence is then passed through the transmitter and looped back through the receiver of the serial interface. The pseudo-random sequence is then descrambled and compared to the input word. Since the input sequence is only a single word rather than a series of words, the comparison is very simple and capable of being performed within the serial interface itself without the need for external test equipment.

Abstract: An apparatus comprising one or more user programmable registers and a circuit configured to compare a predetermined portion of one or more information packets with contents of said one or more user programmable registers.

Abstract: An apparatus generally comprising a plurality of writeable registers, a control circuit, and a transmitter circuit. The writeable registers may be configured to store (i) a first burst value and (ii) a first gap value. The control circuit may be configured to generate an idle signal (i) in a transmit state for a first duration determined by the first burst value and (ii) in an idle state for a second duration determined by the first gap value in response to a first command signal. The transmitter circuit may be configured to (i) enable transmitting while the idle signal is in the transmit state and (ii) disable transmitting while the idle signal is in the idle state.

Abstract: A circuit generally comprising a first circuit and a second circuit. The first circuit may be configured to (i) detect a state of an input signal and (ii) present a plurality of intermediate signals each representative of the state of the input signal during a plurality of clock cycles. The second circuit may be configured to present a filtered signal in response to a selected number of the intermediate signals having a predetermined state.