Patents by Inventor Steven A. Scheer

Steven A. Scheer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180315596
    Abstract: The disclosure herein describes methods for Photosensitized Chemically Amplified Resist Chemicals (PS-CAR) to pattern light sensitive films (e.g., photoresist on anti-reflective coatings) on a semiconductor substrate. In one embodiment, a two-step exposure process may generate higher acid concentration regions within a photoresist layer. The PS-CAR chemicals may include photoacid generators (PAGs) and photosensitizer elements that enhance the decomposition of the PAGs into acid. The first exposure may be a patterned EUV or UV exposure that generates an initial amount of acid and photosensitizer. The second exposure may be a non-EUV flood exposure that excites the photosensitizer which increases the acid generation rate where the photosensitizer is located in the film stack. The distribution of energy during the exposures may be optimized by using certain characteristics (e.g., thickness, index of refraction, doping) of the photoresist layer, an underlying layer, and/or an overlying layer.
    Type: Application
    Filed: July 9, 2018
    Publication date: November 1, 2018
    Inventors: Steven Scheer, Michael A. Carcasi, Benjamen M. Rathsack, Mark H. Somervell, Joshua S. Hooge
  • Patent number: 10020195
    Abstract: The disclosure herein describes methods for Photosensitized Chemically Amplified Resist Chemicals (PS-CAR) to pattern light sensitive films (e.g., photoresist on anti-reflective coatings) on a semiconductor substrate. In one embodiment, a two-step exposure process may generate higher acid concentration regions within a photoresist layer. The PS-CAR chemicals may include photoacid generators (PAGs) and photosensitizer elements that enhance the decomposition of the PAGs into acid. The first exposure may be a patterned EUV or UV exposure that generates an initial amount of acid and photosensitizer. The second exposure may be a non-EUV flood exposure that excites the photosensitizer which increases the acid generation rate where the photosensitizer is located in the film stack. The distribution of energy during the exposures may be optimized by using certain characteristics (e.g., thickness, index of refraction, doping) of the photoresist layer, an underlying layer, and/or an overlying layer.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: July 10, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Steven Scheer, Michael A. Carcasi, Benjamen M. Rathsack, Mark H. Somervell, Joshua S. Hooge
  • Publication number: 20160363868
    Abstract: Disclosed is a method and apparatus for mitigation of photoresist line pattern collapse in a photolithography process by applying a gap-fill material treatment after the post-development line pattern rinse step. The gap-fill material dries into a solid layer filling the inter-line spaces of the line pattern, thereby preventing line pattern collapse due to capillary forces during the post-rinse line pattern drying step. Once dried, the gap-fill material is depolymerized, volatilized, and removed from the line pattern by heating, illumination with ultraviolet light, by application of a catalyst chemistry, or by plasma etching.
    Type: Application
    Filed: July 29, 2016
    Publication date: December 15, 2016
    Inventors: Mark H. SOMERVELL, Benjamen M. RATHSACK, Ian J. BROWN, Steven SCHEER, Joshua S. HOOGE
  • Patent number: 9454081
    Abstract: Disclosed is a method and apparatus for mitigation of photoresist line pattern collapse in a photolithography process by applying a gap-fill material treatment after the post-development line pattern rinse step. The gap-fill material dries into a solid layer filling the inter-line spaces of the line pattern, thereby preventing line pattern collapse due to capillary forces during the post-rinse line pattern drying step. Once dried, the gap-fill material is depolymerized, volatilized, and removed from the line pattern by heating, illumination with ultraviolet light, by application of a catalyst chemistry, or by plasma etching.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: September 27, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Mark H Somervell, Benjamen M Rathsack, Ian J Brown, Steven Scheer, Joshua S Hooge
  • Patent number: 9383138
    Abstract: Methods and heat treatment apparatus for heating a substrate and any layer carried on the substrate during a bake process. A heat exchange gap between the substrate and a heated support is at least partially filled by a gas having a high thermal conductivity. The high thermal conductivity gas is introduced into the heat exchange gap by displacing a lower thermal conductivity originally present in the heat exchange gap when the substrate is loaded. Heat transfer across the heat exchange gap is mediated by the high thermal conductivity gas.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: July 5, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Steven Scheer, Michael A. Carcasi
  • Publication number: 20150241782
    Abstract: The disclosure herein describes methods for Photosensitized Chemically Amplified Resist Chemicals (PS-CAR) to pattern light sensitive films (e.g., photoresist on anti-reflective coatings) on a semiconductor substrate. In one embodiment, a two-step exposure process may generate higher acid concentration regions within a photoresist layer. The PS-CAR chemicals may include photoacid generators (PAGs) and photosensitizer elements that enhance the decomposition of the PAGs into acid. The first exposure may be a patterned EUV or UV exposure that generates an initial amount of acid and photosensitizer. The second exposure may be a non-EUV flood exposure that excites the photosensitizer which increases the acid generation rate where the photosensitizer is located in the film stack. The distribution of energy during the exposures may be optimized by using certain characteristics (e.g., thickness, index of refraction, doping) of the photoresist layer, an underlying layer, and/or an overlying layer.
    Type: Application
    Filed: February 24, 2015
    Publication date: August 27, 2015
    Inventors: Steven SCHEER, Michael A. CARCASI, Benjamen M. RATHSACK, Mark H. SOMERVELL, Joshua S. HOOGE
  • Patent number: 9085045
    Abstract: Provided is a method and system for controlling a spike anneal process on a substrate, comprising selecting one or more objectives, one or more absorbance layers, a technique of modifying absorption of the selected one or more absorbance layers, one or more wavelengths used in a heating device. A substrate modified with the selected technique of modifying absorption is provided. The spike anneal process is performed on the substrate using the selected heating device and selected spike anneal process variables. One or more of the spike anneal process variables, the selected technique of the modifying absorption, the selected one or more wavelengths, and/or the selected heating device are adjusted in order to meet the one or more objectives of the spike anneal process.
    Type: Grant
    Filed: October 28, 2012
    Date of Patent: July 21, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Steven Scheer, Michael A. Carcasi
  • Publication number: 20150125791
    Abstract: Disclosed is a method and apparatus for mitigation of photoresist line pattern collapse in a photolithography process by applying a gap-fill material treatment after the post-development line pattern rinse step. The gap-fill material dries into a solid layer filling the inter-line spaces of the line pattern, thereby preventing line pattern collapse due to capillary forces during the post-rinse line pattern drying step. Once dried, the gap-fill material is depolymerized, volatilized, and removed from the line pattern by heating, illumination with ultraviolet light, by application of a catalyst chemistry, or by plasma etching.
    Type: Application
    Filed: July 3, 2014
    Publication date: May 7, 2015
    Inventors: Mark H. SOMERVELL, Benjamen M. RATHSACK, Ian J. BROWN, Steven SCHEER, Joshua S. HOOGE
  • Patent number: 8795952
    Abstract: Disclosed is a method and apparatus for mitigation of photoresist line pattern collapse in a photolithography process by applying a gap-fill material treatment after the post-development line pattern rinse step. The gap-fill material dries into a solid layer filling the inter-line spaces of the line pattern, thereby preventing line pattern collapse due to capillary forces during the post-rinse line pattern drying step. Once dried, the gap-fill material is depolymerized, volatilized, and removed from the line pattern by heating, illumination with ultraviolet light, by application of a catalyst chemistry, or by plasma etching.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: August 5, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Mark H. Somervell, Benjamen M. Rathsack, Ian J. Brown, Steven Scheer, Joshua Hooge
  • Patent number: 8574810
    Abstract: A method and system for patterning a substrate using a lithographic process, such as a dual tone development process, is described. The method comprises use of at least one photo-activated acid enhancement component to improve process latitude for the dual tone development process.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: November 5, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Carlos A. Fonseca, Mark Somervell, Steven Scheer, Wallace P. Printz
  • Publication number: 20130288487
    Abstract: Provided is a method and system for controlling a spike anneal process on a substrate, comprising selecting one or more objectives, one or more absorbance layers, a technique of modifying absorption of the selected one or more absorbance layers, one or more wavelengths used in a heating device. A substrate modified with the selected technique of modifying absorption is provided. The spike anneal process is performed on the substrate using the selected heating device and selected spike anneal process variables. One or more of the spike anneal process variables, the selected technique of the modifying absorption, the selected one or more wavelengths, and/or the selected heating device are adjusted in order to meet the one or more objectives of the spike anneal process.
    Type: Application
    Filed: October 28, 2012
    Publication date: October 31, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: STEVEN A. SCHEER, MICHAEL CARCASI
  • Patent number: 8568964
    Abstract: A method and system for patterning a substrate using a dual tone development process is described. The method and system comprise a flood exposure of the substrate to improve process latitude for the dual tone development process.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: October 29, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Carlos A. Fonseca, Mark Somervell, Steven Scheer, Wallace P. Printz
  • Patent number: 8449293
    Abstract: A method for patterning a substrate with extreme ultraviolet (EUV) radiation is provided. The method includes contacting a surface of the substrate with at least one surface modification agent that reacts with and bonds to the surface 402 of the substrate 401 to provide a modified surface. A layer of photoresist is formed on the modified surface, followed by exposing the layer of photoresist to a pattern of EUV radiation. The surface modification agent has a general formula: X-L-Z, where X is a leaving group; L is a linkage group including a substituted or un-substituted carbon chain having 1 to 20 carbons, a sulfur moiety, a silicon moiety, or combinations thereof; and Z is at least one of an acid functional group, a photoactive acid generator group or a halide.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: May 28, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Benjamin M. Rathsack, Steven Scheer, Mark H. Somervell
  • Patent number: 8288174
    Abstract: An Electrostatic Post Exposure Bake (EPEB) subsystem comprising an Electrostatic Bake Plate (EBP) configured in a processing chamber in an EPEB subsystem, wherein the EPEB wafer comprises an exposed masking layer having unexposed regions and exposed regions therein and the EPEB wafer is developed using the EBP.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: October 16, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Benjamen M. Rathsack, Brian Head, Steven Scheer
  • Patent number: 8283111
    Abstract: A method of patterning a substrate using a dual-tone development process is described. The patterning method comprises forming a layer of radiation-sensitive material on a substrate, wherein the layer of radiation-sensitive material comprises a dual tone resist. Thereafter, the patterning method comprises performing one or more exposures of the layer of radiation-sensitive material to one or more patterns of radiation, wherein at least one of the one or more exposures comprises using a mask having a dual-tone mask pattern region configured for printing dual tone features and a half-tone mask pattern region configured for printing half-tone features. Furthermore, the half-tone mask pattern region is optimized for use with the dual tone resist.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: October 9, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Carlos A. Fonseca, Mark Somervell, Steven Scheer
  • Publication number: 20120244645
    Abstract: An Electrostatic Post Exposure Bake (EPEB) subsystem comprising an Electrostatic Bake Plate (EBP) configured in a processing chamber in an EPEB subsystem, wherein the EPEB wafer comprises an exposed masking layer having unexposed regions and exposed regions therein and the EPEB wafer is developed using the EBP.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 27, 2012
    Applicant: Tokyo Electron Limited
    Inventors: Benjamen M. Rathsack, Brian Head, Steven Scheer
  • Patent number: 8257911
    Abstract: A method for patterning a substrate is described. In particular, the invention relates to a method for double patterning a substrate using dual tone development. Further, the invention relates to optimizing a dual tone development process.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: September 4, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Roel Gronheid, Sophie Bernard, Carlos A. Fonseca, Mark Somervell, Steven Scheer
  • Patent number: 8197996
    Abstract: A method and system for patterning a substrate using a dual-tone development process is described. The method and system comprise using a resist material having a polymer backbone with a plurality of protecting groups attached thereto to improve process latitude and critical dimension uniformity for the dual-tone development process.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: June 12, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Carlos A. Fonseca, Mark Somervell, Steven Scheer
  • Patent number: 8129080
    Abstract: A method and system for patterning a substrate using a dual-tone development process is described. The method and system comprise using a resist material having a polymer backbone with a plurality of protecting groups attached thereto to improve process latitude and critical dimension uniformity for the dual-tone development process.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: March 6, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Carlos A. Fonseca, Mark Somervell, Steven Scheer
  • Publication number: 20120045721
    Abstract: The invention can provide a method of processing a substrate using Double-Patterned-Shadow (D-P-S) processing sequences that can include (D-P-S) creation procedures, (D-P-S) evaluation procedures, and (D-P-S) transfer sequences. The (D-P-S) creation procedures can include deposition procedures, activation procedures, de-protecting procedures, sidewall angle (SWA) correction procedure, and Double Patterned (DP) developing procedures.
    Type: Application
    Filed: August 18, 2010
    Publication date: February 23, 2012
    Applicant: Tokyo Electron Limited
    Inventors: Wallace P. Printz, Steven Scheer