Abstract: Disclosed are novel methods and apparatus for efficiently providing power buses and bump patterns with reduced inductance and/or resistance. In an embodiment, an apparatus is disclosed. The apparatus includes a plurality of power and ground bus pairs. Each power and ground bus pair may have a power bus and a ground bus. The apparatus further includes a first power bus from a first pair of the plurality of power and ground bus pairs. The first power bus may include a plurality of power bumps. The apparatus also includes a first ground bus from the first pair of the plurality of power and ground bus pairs. The first ground bus may include a plurality of ground bumps. Each of the plurality of power/ground bumps may be substantially equidistance from any immediately neighboring ground bump of the first ground bus.

Abstract: Disclosed are novel methods and apparatus for efficiently providing power buses and bump patterns with reduced inductance and/or resistance. In an embodiment, an apparatus is disclosed. The apparatus includes a plurality of power and ground bus pairs. Each power and ground bus pair may have a power bus and a ground bus. The apparatus further includes a first power bus from a first pair of the plurality of power and ground bus pairs. The first power bus may include a plurality of power bumps. The apparatus also includes a first ground bus from the first pair of the plurality of power and ground bus pairs. The first ground bus may include a plurality of ground bumps. Each of the plurality of power/ground bumps may be substantially equidistance from any immediately neighboring ground bump of the first ground bus.

Abstract: A system for testing a high speed integrated circuit includes a test device having a test clock with a first maximum frequency for performing level sensitive scan design (LSSD) testing of the integrated circuit device under test, a frequency multiplier circuit for multiplying the test clock signal to a higher second frequency capable of operating the device under test, and a finite state machine for generating a first internal clock for testing the device under test. In a practical embodiment, the internal clock speed may be running at a frequency many multiples of the test clock.

Abstract: A machine and method for separating chip-like particles according to thickness which provides low blinding and high efficiency at high throughput in sustained operation. The machine has a sloping deck mounting a series of spaced flexible louvers or slats which extend parallel to the direction of chip flow down the deck. The slats are canted transversely to the direction of flow, and present unobstructed full length slot-like chip openings between them. The deck is driven with a horizontal gyratory motion such that during the upstream half of each cycle of movement, each slot moves toward chips on the adjacent slat which slopes toward it, and moves away from such chips during the downstream half of the cycle. The path of screening movement is uniform over the entire deck, that is, the motion of the lower or discharge end of the deck matches that of the upper or feed end.